Message ID | 20230913-gpll_cleanup-v2-6-c8ceb1a37680@quicinc.com (mailing list archive) |
---|---|
State | Not Applicable, archived |
Headers | show |
Series | Add GPLL0 as clock provider for the Qualcomm's IPQ mailbox controller | expand |
diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index d2e25ff6db7f..a38413f8d132 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -125,10 +125,12 @@ allOf: items: - description: primary pll parent of the clock driver - description: XO clock + - description: GCC GPLL0 clock source clock-names: items: - const: pll - const: xo + - const: gpll0 - if: properties: