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[3/8] dt-bindings: clock: ipq5332: add definition for GPLL0_OUT_AUX clock

Message ID 20231030-ipq5332-nsscc-v1-3-6162a2c65f0a@quicinc.com (mailing list archive)
State Awaiting Upstream, archived
Headers show
Series Add NSS clock controller support for IPQ5332 | expand

Commit Message

Kathiravan Thirumoorthy Oct. 30, 2023, 9:47 a.m. UTC 
Add the definition for GPLL0_OUT_AUX clock.

Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
 include/dt-bindings/clock/qcom,ipq5332-gcc.h | 1 +
 1 file changed, 1 insertion(+)

Comments

Krzysztof Kozlowski Oct. 30, 2023, 11:08 a.m. UTC | #1 
On 30/10/2023 10:47, Kathiravan Thirumoorthy wrote:
> Add the definition for GPLL0_OUT_AUX clock.
> 
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> ---
>  include/dt-bindings/clock/qcom,ipq5332-gcc.h | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
index 4649026da332..486b6cf2e916 100644
--- a/include/dt-bindings/clock/qcom,ipq5332-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
@@ -176,6 +176,7 @@ 
 #define GCC_PCIE3X1_0_PIPE_CLK_SRC			170
 #define GCC_PCIE3X1_1_PIPE_CLK_SRC			171
 #define GCC_USB0_PIPE_CLK_SRC				172
+#define GPLL0_OUT_AUX					173
 
 #define GCC_ADSS_BCR					0
 #define GCC_ADSS_PWM_CLK_ARES				1