From patchwork Mon Dec 11 22:45:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 13488178 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="z0HC5gj5" Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9DDED9 for ; Mon, 11 Dec 2023 14:46:15 -0800 (PST) Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-54cfb03f1a8so6686382a12.2 for ; Mon, 11 Dec 2023 14:46:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702334774; x=1702939574; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=wCLPI7bH+3S27i/ILivETHCwTpYXRhVoatws0XCHn9U=; b=z0HC5gj5mMISBJgMoSEBEDECL+yjGp8rKN6GB3QIyfp1iTFPjKWIJiCR4hSJFsHwxx Slf26vinpBvDIuOi1VxFOai2Ed8/2Xjsa4GcQ7jxhwi+ohsuZFiFNwIgBH5ryzkQBN/M 98hxbYp/mbarSAXq1omsncd5QmqDHHDZogN9vHe7XNQ/GMUMnCZfBoabpGnIl7WzPt3o 6TLQYttyyRr4Lob6OPwM2esNTCL6aj9N/od6skeOexeeO8+23CtZgX601RA5vuxIY0E3 YY4pQ67Y30GOQwB1Eq5o7eUQHyZbFqRZQJ/uf5ibtkavvjyM0lpk3RtkZEPfXCrDVlUa ACtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702334774; x=1702939574; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wCLPI7bH+3S27i/ILivETHCwTpYXRhVoatws0XCHn9U=; b=kzy0luB1WuSHqm1DH9P7RbYybdMhPEEMlCOQCaZtqk9GUqRsgNz4B9DfvXZd48nwq3 ole1DnxI+Z8/hGNkLPfGnyXnp+Tf4LvAGmwtHOf61p3BRJf7hYMZMNWJAl3RfxfW7HC+ c46FGzTcAeA7SsBo7dxCJZ2P2lLx8Sl7jDs7M0rFiM9Wv/nPO6fo+xs6WKseWQjLEVNv kA49EylgYoRno6nbLBnag72rXTkjzWo6HEKpEHMXKubfvwA2QL7swobKvdOj91u5gGAH c6bVMLJHATmP0kJHT1P2hnxWs1jxMo6hkKOwrWO7qMr+55sCNXCnCiXgms4L++CSJkM6 PVDQ== X-Gm-Message-State: AOJu0YzztfYpg/aeG2WHB9ZKC+y7CUVP5z3aygxWUW8mf16tgy0HpCfu 2tPM0khtFNo61+41itGYcZkj/w== X-Google-Smtp-Source: AGHT+IFf3TFH3Vq8IqCVrsc10vqAtg/huwnES61DvJq6mhKHgfkX2oXYrK/cvtToGG0f3G0hT9s47w== X-Received: by 2002:a50:871e:0:b0:54d:712c:2323 with SMTP id i30-20020a50871e000000b0054d712c2323mr2601746edb.16.1702334774393; Mon, 11 Dec 2023 14:46:14 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id if3-20020a0564025d8300b0054afcab0af2sm4091789edb.59.2023.12.11.14.46.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Dec 2023 14:46:14 -0800 (PST) From: Abel Vesa Date: Tue, 12 Dec 2023 00:45:42 +0200 Subject: [PATCH 02/10] dt-bindings: clock: qcom: Document the X1E80100 Display Clock Controller Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231212-x1e80100-clock-controllers-v1-2-0de1af44dcb3@linaro.org> References: <20231212-x1e80100-clock-controllers-v1-0-0de1af44dcb3@linaro.org> In-Reply-To: <20231212-x1e80100-clock-controllers-v1-0-0de1af44dcb3@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Neil Armstrong , Vladimir Zapolskiy Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa , Rajendra Nayak X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=5335; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=SR7cwWuwrAzLkn1MdxMzxwbh9Ip0B4d2L9ip2mgk18A=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBld5ElvntL5DjE5bE9JnkZCvgb3D0JAiPu5uEJr 9TK0gSzNBiJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZXeRJQAKCRAbX0TJAJUV VqgvD/9gCOqnm7FjMy7a66PkaedEj3x8CuE+N+6Le8kxaX09lP47H5L22QclKysKew+NhQHR5ly UGD6swtRaei5NC80MkbhKybk1JsEDC3Dmgx7c0CH4snJ/qZc6gcJeKUNe7H+xMo3M+8lwEedXfy 4Ip5QCEQ2fgrF165wsidv6edP2JoHADj5c6QtSYURzqoctGVNKZdJJGt3s+ldD7/myEPuAiInFt DA4n4TmWKkfa9Q7CilUEtn2kQH4XC/skhBM416dE3voK8LoS4AUiR/rk+CG0M47BJ1Q2W31/sI+ y1/OR4aL49bfTOL3N2vktnIHqRYOybOVs/mHP88Nwghb6rJ9qBMMUK6WCg3VoS4SjreMganAn6V DE2Lh7/zGQ+YRRIxyyFkKkBb5F2qPN5O6ri7wbxULPt1QBGAVCg2XgimflPd/9NX57zMJ+cC3Yc v3l9mt1aGUyaZr5u2VtYyHmb2bKX/jQqAi0JNtansbpRMxvoWp6ehI61NwXXPBbzT3injOtKESI fKZgg0cp4OttuQhCMnu87PW32x2JFjRHRMkYkaPtG1SnPM7ZPr1cZEnH0yfXjLrTiWRCGT6bDNr cKNoiwfeWAeaiT46Ya/isgfnT+Agmn2fPedyKIVscM3QdGu3hIle8ln8eaRdPzs3bG47cUQTr1H qrVsEzoEkyQGwCQ== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE From: Rajendra Nayak Add bindings documentation for the X1E80100 Display Clock Controller. Signed-off-by: Rajendra Nayak Signed-off-by: Abel Vesa --- .../bindings/clock/qcom,sm8550-dispcc.yaml | 2 + include/dt-bindings/clock/qcom,x1e80100-dispcc.h | 98 ++++++++++++++++++++++ 2 files changed, 100 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml index 369a0491f8d6..bad0260764d4 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml @@ -17,12 +17,14 @@ description: | See also: - include/dt-bindings/clock/qcom,sm8550-dispcc.h - include/dt-bindings/clock/qcom,sm8650-dispcc.h + - include/dt-bindings/clock/qcom,x1e80100-dispcc.h properties: compatible: enum: - qcom,sm8550-dispcc - qcom,sm8650-dispcc + - qcom,x1e80100-dispcc clocks: items: diff --git a/include/dt-bindings/clock/qcom,x1e80100-dispcc.h b/include/dt-bindings/clock/qcom,x1e80100-dispcc.h new file mode 100644 index 000000000000..6bbb5c2d0b16 --- /dev/null +++ b/include/dt-bindings/clock/qcom,x1e80100-dispcc.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC_H +#define _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC_H + +/* DISP_CC clocks */ +#define DISP_CC_MDSS_ACCU_CLK 0 +#define DISP_CC_MDSS_AHB1_CLK 1 +#define DISP_CC_MDSS_AHB_CLK 2 +#define DISP_CC_MDSS_AHB_CLK_SRC 3 +#define DISP_CC_MDSS_BYTE0_CLK 4 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 5 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 7 +#define DISP_CC_MDSS_BYTE1_CLK 8 +#define DISP_CC_MDSS_BYTE1_CLK_SRC 9 +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10 +#define DISP_CC_MDSS_BYTE1_INTF_CLK 11 +#define DISP_CC_MDSS_DPTX0_AUX_CLK 12 +#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13 +#define DISP_CC_MDSS_DPTX0_LINK_CLK 14 +#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 15 +#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 16 +#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 17 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 18 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 19 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 20 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 21 +#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 22 +#define DISP_CC_MDSS_DPTX1_AUX_CLK 23 +#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 24 +#define DISP_CC_MDSS_DPTX1_LINK_CLK 25 +#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 26 +#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 27 +#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 28 +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 29 +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 30 +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 31 +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 32 +#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 33 +#define DISP_CC_MDSS_DPTX2_AUX_CLK 34 +#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 35 +#define DISP_CC_MDSS_DPTX2_LINK_CLK 36 +#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 37 +#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 38 +#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 39 +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 40 +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 41 +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 42 +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 43 +#define DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK 44 +#define DISP_CC_MDSS_DPTX3_AUX_CLK 45 +#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 46 +#define DISP_CC_MDSS_DPTX3_LINK_CLK 47 +#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 48 +#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 49 +#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 50 +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 51 +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 52 +#define DISP_CC_MDSS_ESC0_CLK 53 +#define DISP_CC_MDSS_ESC0_CLK_SRC 54 +#define DISP_CC_MDSS_ESC1_CLK 55 +#define DISP_CC_MDSS_ESC1_CLK_SRC 56 +#define DISP_CC_MDSS_MDP1_CLK 57 +#define DISP_CC_MDSS_MDP_CLK 58 +#define DISP_CC_MDSS_MDP_CLK_SRC 59 +#define DISP_CC_MDSS_MDP_LUT1_CLK 60 +#define DISP_CC_MDSS_MDP_LUT_CLK 61 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 62 +#define DISP_CC_MDSS_PCLK0_CLK 63 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 64 +#define DISP_CC_MDSS_PCLK1_CLK 65 +#define DISP_CC_MDSS_PCLK1_CLK_SRC 66 +#define DISP_CC_MDSS_RSCC_AHB_CLK 67 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 68 +#define DISP_CC_MDSS_VSYNC1_CLK 69 +#define DISP_CC_MDSS_VSYNC_CLK 70 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 71 +#define DISP_CC_PLL0 72 +#define DISP_CC_PLL1 73 +#define DISP_CC_SLEEP_CLK 74 +#define DISP_CC_SLEEP_CLK_SRC 75 +#define DISP_CC_XO_CLK 76 +#define DISP_CC_XO_CLK_SRC 77 + +/* DISP_CC resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_CORE_INT2_BCR 1 +#define DISP_CC_MDSS_RSCC_BCR 2 + +/* DISP_CC GDSCR */ +#define DISP_CC_MDSS_CORE_GDSC 0 +#define DISP_CC_MDSS_CORE_INT2_GDSC 1 + +#endif