From patchwork Thu Dec 14 16:49:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 13493275 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="xg13y4Ek" Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36ABD121 for ; Thu, 14 Dec 2023 08:50:09 -0800 (PST) Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-a1f0616a15bso958243266b.2 for ; Thu, 14 Dec 2023 08:50:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702572607; x=1703177407; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=YVNXxg+9nL5wJKIK1np/vV0mTD7W9fQ7IDNoTCiFtT4=; b=xg13y4EkPv/leP0sgCzYELXEbk3TuDxhPnNRCHAcZTnYST4fVsPdCUGq9sIG4sHjiA B8IaerKs2Lva07k5rUnrsI8S3oZQp3Z7xBn/z7RemXRJJy9uo1qTXF39STCkC8uUtZep YspDgMiayLTh7XabeMfbFtofkc5Dae4XlMbTtP8JAjkBVmoWzXJFRfhgxSESJ+6nuN5q 3Km+t1XPRE/v9nikZyBNLSIWMG4R3IgDIUl+nKUEOfXAc/v3qz6XzCvsPF4qudi6yVBN /bkuNCZxsNMlrg02JOcgV27rdXxxHvGpT4wQ+qctORjgtBuRl8pHc5L7m6n51zgg0ykO gCKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702572607; x=1703177407; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YVNXxg+9nL5wJKIK1np/vV0mTD7W9fQ7IDNoTCiFtT4=; b=sQMdG+5ip7ONPZWnulSPtFMNIUMHbYuvF6yurrFee6V4ZfM/CmpIXjxWz+Tt4bezEm +aWCZYoUAJE7tSYHzfkKdkzCqxe6O6XZGmGF/gZBvGsyg+O7Eoyd42A+gpF5UajjxZqH e3F5b1qPgiBsjqHVDjaclcZhFyOkwclYRYqmDypf+zy3GK3WDoee3oT17lNVbjfNh/wC jBJvZtVJJdp7XjA4HluxX2ca2ZYfXRQ+RYDElJPFVFpVX4YNKY9f25XVHCsg3izoSEXS orsQtfJiehzecvGwDiZzUUxy1RFPGfgBRbNwkYOucVvYiMZ7NjpANrvuY0+Obm5q3Bru +DyA== X-Gm-Message-State: AOJu0YwCt1OFnTT9JTWUjnRQVikpcldcdEj9OGpo6vSYAsZ4CK/ZeRZR eusn45YcZeW5jEIocrIZGP5uwA== X-Google-Smtp-Source: AGHT+IFjNqeKsYaZC4DeK0s39Vq559/OpBQMBEIddm7hKaejJvB8yT5aOMEVFYwS7ckfQz+zFM4P8w== X-Received: by 2002:a17:906:5a49:b0:9e0:4910:166a with SMTP id my9-20020a1709065a4900b009e04910166amr5931126ejc.32.1702572607724; Thu, 14 Dec 2023 08:50:07 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id tn9-20020a170907c40900b00a1f7ab65d3fsm8530308ejc.131.2023.12.14.08.50.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 08:50:07 -0800 (PST) From: Abel Vesa Date: Thu, 14 Dec 2023 18:49:35 +0200 Subject: [PATCH v2 06/10] clk: qcom: clk-alpha-pll: Add support for zonda ole pll configure Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231214-x1e80100-clock-controllers-v2-6-2b0739bebd27@linaro.org> References: <20231214-x1e80100-clock-controllers-v2-0-2b0739bebd27@linaro.org> In-Reply-To: <20231214-x1e80100-clock-controllers-v2-0-2b0739bebd27@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Neil Armstrong , Vladimir Zapolskiy , Dmitry Baryshkov Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa , Rajendra Nayak X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=3693; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=pUaL0S9mlmI81sPMJsRfFAirIeeYUm7HXjGy1jinNxQ=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBlezIuJBT7gvPwd62+qbc80TrUa/uh0Vq6qT2fX QsjsuBAW1OJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZXsyLgAKCRAbX0TJAJUV VtVWEAC2Q9GN+p2UCaHWVOGj5g9qRarYVsAWjFKr4ic8b2WVOaMGWLb513XMqshxoMLlqiglbHp WTDFpl8ThRTTp7NYQ5ovUlvXIremYracN8PrIcE0PQMYJOMBNs5rZYVqIE2rJjkmLNwQq1KuYhg 9mK5a20cCwvXA3OhPgLUvsQKEv6FFxcEUEPtDkN/3Jij7SUkXtysBbEKUdSQlc36cfsHXovF6Ul +hFrmFVinE9jUsf+2FRJA0r0pmCgaXFc2iXDdKVUhgwvAls9dG7rzSkz87sqkHz9cfAmB7yvMqn 2VZp7lk+WO3pSakn0S43Dk5xDyGvPQYZ4U9ty8NOaAcjhNQXSsRchk67bHnu20q5drdfnsRMCl5 UmZTz2YYhwJch1dLOscW3rJFQwU5VLf2RiK/XKGkbVP5VcsUxaDgzymY6EMAKCOguZHSQeW170H I9ktHMKv3vhDoQUIMDXJ6MsZelL19ZV52h64EP57ymFx3YBikQroursoWkEDrXU7ylI7xu8BYR8 tOgsc2MwDSOCDnDk2Qfdhk06aZVN1a6n+SdykGBV9ErbKxpEr39kP3r1bkUUg3+w44YLznHSQRh t4+g2Q+b00lE4v+q/lNrQlV2IZu4c052kGjEmQ7u5+aU8usR1ehCxnsJNlMjkQNhvyKe/fAeIE2 0Zhguy+m1FUJklw== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE From: Rajendra Nayak Zonda ole pll has as extra PLL_OFF_CONFIG_CTL_U2 register, hence add support for it. Signed-off-by: Rajendra Nayak Signed-off-by: Abel Vesa --- drivers/clk/qcom/clk-alpha-pll.c | 26 ++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 4 ++++ 2 files changed, 30 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 05898d2a8b22..85f8e2ad0b37 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -52,6 +52,7 @@ #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1]) +#define PLL_CONFIG_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U2]) #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1]) @@ -228,6 +229,21 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_ALPHA_VAL] = 0x24, [PLL_OFF_ALPHA_VAL_U] = 0x28, }, + [CLK_ALPHA_PLL_TYPE_ZONDA_OLE] = { + [PLL_OFF_L_VAL] = 0x04, + [PLL_OFF_ALPHA_VAL] = 0x08, + [PLL_OFF_USER_CTL] = 0x0c, + [PLL_OFF_USER_CTL_U] = 0x10, + [PLL_OFF_CONFIG_CTL] = 0x14, + [PLL_OFF_CONFIG_CTL_U] = 0x18, + [PLL_OFF_CONFIG_CTL_U1] = 0x1c, + [PLL_OFF_CONFIG_CTL_U2] = 0x20, + [PLL_OFF_TEST_CTL] = 0x24, + [PLL_OFF_TEST_CTL_U] = 0x28, + [PLL_OFF_TEST_CTL_U1] = 0x2c, + [PLL_OFF_OPMODE] = 0x30, + [PLL_OFF_STATUS] = 0x3c, + }, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); @@ -2093,6 +2109,16 @@ const struct clk_ops clk_alpha_pll_zonda_ops = { }; EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); +const struct clk_ops clk_alpha_pll_zonda_ole_ops = { + .enable = clk_zonda_pll_enable, + .disable = clk_zonda_pll_disable, + .is_enabled = clk_trion_pll_is_enabled, + .recalc_rate = clk_trion_pll_recalc_rate, + .round_rate = clk_alpha_pll_round_rate, + .set_rate = clk_zonda_pll_set_rate, +}; +EXPORT_SYMBOL(clk_alpha_pll_zonda_ole_ops); + void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) { diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index a1a75bb12fe8..99a3db9de4a1 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -21,6 +21,7 @@ enum { CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION, CLK_ALPHA_PLL_TYPE_AGERA, CLK_ALPHA_PLL_TYPE_ZONDA, + CLK_ALPHA_PLL_TYPE_ZONDA_OLE, CLK_ALPHA_PLL_TYPE_LUCID_EVO, CLK_ALPHA_PLL_TYPE_LUCID_OLE, CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, @@ -42,6 +43,7 @@ enum { PLL_OFF_CONFIG_CTL, PLL_OFF_CONFIG_CTL_U, PLL_OFF_CONFIG_CTL_U1, + PLL_OFF_CONFIG_CTL_U2, PLL_OFF_TEST_CTL, PLL_OFF_TEST_CTL_U, PLL_OFF_TEST_CTL_U1, @@ -119,6 +121,7 @@ struct alpha_pll_config { u32 config_ctl_val; u32 config_ctl_hi_val; u32 config_ctl_hi1_val; + u32 config_ctl_hi2_val; u32 user_ctl_val; u32 user_ctl_hi_val; u32 user_ctl_hi1_val; @@ -173,6 +176,7 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops; extern const struct clk_ops clk_alpha_pll_zonda_ops; #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops +extern const struct clk_ops clk_alpha_pll_zonda_ole_ops; extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;