| Message ID | 20240103-topic-845gdsc-v1-1-368efbe1a61d@linaro.org (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | clk: qcom: dispcc-sdm845: Adjust internal GDSC wait times | expand |
On 03/01/2024 20:20, Konrad Dybcio wrote: > SDM845 downstream uses non-default values for GDSC internal waits. > Program them accordingly to avoid surprises. > > Fixes: 81351776c9fb ("clk: qcom: Add display clock controller driver for SDM845") > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> This doesn't break anything, but I'm not exactly sure what it fixes :P Tested-by: Caleb Connolly <caleb.connolly@linaro.org> # OnePlus 6 > --- > drivers/clk/qcom/dispcc-sdm845.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c > index 735adfefc379..e792e0b130d3 100644 > --- a/drivers/clk/qcom/dispcc-sdm845.c > +++ b/drivers/clk/qcom/dispcc-sdm845.c > @@ -759,6 +759,8 @@ static struct clk_branch disp_cc_mdss_vsync_clk = { > > static struct gdsc mdss_gdsc = { > .gdscr = 0x3000, > + .en_few_wait_val = 0x6, > + .en_rest_wait_val = 0x5, > .pd = { > .name = "mdss_gdsc", > }, > > --- > base-commit: 0fef202ac2f8e6d9ad21aead648278f1226b9053 > change-id: 20240103-topic-845gdsc-bcd9d549f153 > > Best regards,
On Wed, 03 Jan 2024 21:20:18 +0100, Konrad Dybcio wrote: > SDM845 downstream uses non-default values for GDSC internal waits. > Program them accordingly to avoid surprises. > > Applied, thanks! [1/1] clk: qcom: dispcc-sdm845: Adjust internal GDSC wait times commit: 117e7dc697c2739d754db8fe0c1e2d4f1f5d5f82 Best regards,
diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c index 735adfefc379..e792e0b130d3 100644 --- a/drivers/clk/qcom/dispcc-sdm845.c +++ b/drivers/clk/qcom/dispcc-sdm845.c @@ -759,6 +759,8 @@ static struct clk_branch disp_cc_mdss_vsync_clk = { static struct gdsc mdss_gdsc = { .gdscr = 0x3000, + .en_few_wait_val = 0x6, + .en_rest_wait_val = 0x5, .pd = { .name = "mdss_gdsc", },
SDM845 downstream uses non-default values for GDSC internal waits. Program them accordingly to avoid surprises. Fixes: 81351776c9fb ("clk: qcom: Add display clock controller driver for SDM845") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- drivers/clk/qcom/dispcc-sdm845.c | 2 ++ 1 file changed, 2 insertions(+) --- base-commit: 0fef202ac2f8e6d9ad21aead648278f1226b9053 change-id: 20240103-topic-845gdsc-bcd9d549f153 Best regards,