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[178.235.179.81]) by smtp.gmail.com with ESMTPSA id bs18-20020a170906d1d200b00a2808ee8ab1sm3892978ejb.150.2024.01.08.04.33.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 04:33:02 -0800 (PST) From: Konrad Dybcio Date: Mon, 08 Jan 2024 13:32:35 +0100 Subject: [PATCH 18/18] clk: qcom: videocc-sm8550: Set delay for Venus CLK resets Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240105-topic-venus_reset-v1-18-981c7a624855@linaro.org> References: <20240105-topic-venus_reset-v1-0-981c7a624855@linaro.org> In-Reply-To: <20240105-topic-venus_reset-v1-0-981c7a624855@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue , Dikshita Agarwal , Vikash Garodia , Konrad Dybcio , Manivannan Sadhasivam X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704717148; l=986; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=nUkji27joUy4z7sSoyVsNLtQaWjmCqTk31+xfHWXM8I=; b=w4g8AeDrPElFZuWnShULIUezl/D8Mown8pWJMvSQi8+U6rX64xETD1nQ/r4IjQuIvmP9ljfUk P7na2O9tyb4B4xcuvQv5tDQcZWCiODy4K8z0qMFVpLRR81QOZKxrfOy X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Some Venus resets may require more time when toggling. Describe that. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/videocc-sm8550.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c index f3c9dfaee968..e3f146347da7 100644 --- a/drivers/clk/qcom/videocc-sm8550.c +++ b/drivers/clk/qcom/videocc-sm8550.c @@ -378,8 +378,8 @@ static const struct qcom_reset_map video_cc_sm8550_resets[] = { [CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 }, [CVP_VIDEO_CC_MVS1_BCR] = { 0x80c8 }, [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 }, - [VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 }, - [VIDEO_CC_MVS1C_CLK_ARES] = { 0x8090, 2 }, + [VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 }, + [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x8090, .bit = 2, .udelay = 1000 }, }; static const struct regmap_config video_cc_sm8550_regmap_config = {