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[37.8.245.233]) by smtp.gmail.com with ESMTPSA id un9-20020a170907cb8900b00a384365e3b9sm562305ejc.195.2024.02.06.10.44.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Feb 2024 10:44:04 -0800 (PST) From: Konrad Dybcio Date: Tue, 06 Feb 2024 19:43:50 +0100 Subject: [PATCH v2 17/18] clk: qcom: videocc-sm8450: Set delay for Venus CLK resets Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240105-topic-venus_reset-v2-17-c37eba13b5ce@linaro.org> References: <20240105-topic-venus_reset-v2-0-c37eba13b5ce@linaro.org> In-Reply-To: <20240105-topic-venus_reset-v2-0-c37eba13b5ce@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue , Dikshita Agarwal , Vikash Garodia , Manivannan Sadhasivam , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1707245017; l=1158; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=zaeCrdSIZdnQrOpfJSqYQ9Ck7vw9+mDCXs61VSh8KsU=; b=gAjYN4kZvcLr/Jv2d1Ru1N8PYvkeDBd1lv8wL36Fm8wIxdb5F/6CFQKx+SJAI+jQjzqqSJPKn K9LFK1EAOleDa6zshRxR50X2VJYvve/1+D2EdEHxnFwyUdQbu8kFanZ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Some Venus resets may require more time when toggling. Describe that. The value is known for SM8450, see [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/d0730ea5867264ee50b793f6700eb6a376ddcbbb Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/videocc-sm8450.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-sm8450.c index 16a61146e619..67ca302a0737 100644 --- a/drivers/clk/qcom/videocc-sm8450.c +++ b/drivers/clk/qcom/videocc-sm8450.c @@ -373,8 +373,8 @@ static const struct qcom_reset_map video_cc_sm8450_resets[] = { [CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 }, [CVP_VIDEO_CC_MVS1_BCR] = { 0x80bc }, [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8070 }, - [VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 }, - [VIDEO_CC_MVS1C_CLK_ARES] = { 0x808c, 2 }, + [VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 }, + [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x808c, .bit = 2, .udelay = 1000 }, }; static const struct regmap_config video_cc_sm8450_regmap_config = {