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[37.8.245.233]) by smtp.gmail.com with ESMTPSA id un9-20020a170907cb8900b00a384365e3b9sm562305ejc.195.2024.02.06.10.43.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Feb 2024 10:43:43 -0800 (PST) From: Konrad Dybcio Date: Tue, 06 Feb 2024 19:43:36 +0100 Subject: [PATCH v2 03/18] clk: qcom: reset: Ensure write completion on reset de/assertion Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240105-topic-venus_reset-v2-3-c37eba13b5ce@linaro.org> References: <20240105-topic-venus_reset-v2-0-c37eba13b5ce@linaro.org> In-Reply-To: <20240105-topic-venus_reset-v2-0-c37eba13b5ce@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue , Dikshita Agarwal , Vikash Garodia , Manivannan Sadhasivam , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1707245017; l=1253; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=XwCgSZpLR0e1PPyOXyw9iz+BwYBf4ZHexOSsfIVdxQU=; b=Tq60ALVlciDLkdivYsIcmrQF748EJR+pUE1IufXNafFGsZuOAbb9f/rPSAB0nnwQSqzg3qqQb 6l7lLfFExgEDOXPfLnpXb/GSuu3ptYAHeuizJ30cBnCMswdh1J1/Bz5 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Trying to toggle the resets in a rapid fashion can lead to the changes not actually arriving at the clock controller block when we expect them to. This was observed at least on SM8250. Read back the value after regmap_update_bits to ensure write completion. Fixes: db1029814f1f ("clk: qcom: reset: Ensure write completion on reset de/assertion") Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/reset.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/reset.c b/drivers/clk/qcom/reset.c index 20d1d35aaf22..d96c96a9089f 100644 --- a/drivers/clk/qcom/reset.c +++ b/drivers/clk/qcom/reset.c @@ -33,7 +33,12 @@ static int qcom_reset_set_assert(struct reset_controller_dev *rcdev, map = &rst->reset_map[id]; mask = map->bitmask ? map->bitmask : BIT(map->bit); - return regmap_update_bits(rst->regmap, map->reg, mask, assert ? mask : 0); + regmap_update_bits(rst->regmap, map->reg, mask, assert ? mask : 0); + + /* Read back the register to ensure write completion, ignore the value */ + regmap_read(rst->regmap, map->reg, &mask); + + return 0; } static int qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)