Message ID | 20240201161258.1013664-6-andre.draszik@linaro.org (mailing list archive) |
---|---|
State | Not Applicable, archived |
Headers | show |
Series | gs101 oriole: peripheral block 1 (peric1) and i2c12 support | expand |
On Thu, 01 Feb 2024 16:11:41 +0000, André Draszik wrote: > Enable the cmu-peric1 clock controller. It feeds additional USI, I3C > and PWM interfaces / busses. > > Note that &sysreg_peric1 needs a clock to be able to access its > registers and now that Linux knows about this clock, we need to add it > in this commit as well so as to keep &sysreg_peric1 working, so that > the clock can be enabled as and when needed. > > [...] Applied, thanks! [5/7] arm64: dts: exynos: gs101: enable cmu-peric1 clock controller https://git.kernel.org/krzk/linux/c/7d66d98b5bf376a999df13c65bbc0aac3cc9de02 Best regards,
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index aaac04df5e65..e1bcf490309a 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -429,9 +429,20 @@ serial_0: serial@10a00000 { }; }; + cmu_peric1: clock-controller@10c00000 { + compatible = "google,gs101-cmu-peric1"; + reg = <0x10c00000 0x4000>; + #clock-cells = <1>; + clocks = <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; + clock-names = "oscclk", "bus", "ip"; + }; + sysreg_peric1: syscon@10c20000 { compatible = "google,gs101-peric1-sysreg", "syscon"; reg = <0x10c20000 0x10000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK>; }; pinctrl_peric1: pinctrl@10c40000 {