@@ -58,6 +58,27 @@
#define HISTB_USB3_UTMI_CLK1 48
#define HISTB_USB3_PIPE_CLK1 49
#define HISTB_USB3_SUSPEND_CLK1 50
+#define HISTB_SDIO1_BIU_CLK 51
+#define HISTB_SDIO1_CIU_CLK 52
+#define HISTB_SDIO1_DRV_CLK 53
+#define HISTB_SDIO1_SAMPLE_CLK 54
+#define HISTB_ETH0_PHY_CLK 55
+#define HISTB_ETH1_PHY_CLK 56
+#define HISTB_WDG0_CLK 57
+#define HISTB_USB2_UTMI0_CLK HISTB_USB2_UTMI_CLK
+#define HISTB_USB2_UTMI1_CLK 58
+#define HISTB_USB3_REF_CLK 59
+#define HISTB_USB3_GM_CLK 60
+#define HISTB_USB3_GS_CLK 61
+
+/* Hi3798MV200 specific clocks */
+
+// reuse clocks of histb
+#define HI3798MV200_GMAC_CLK HISTB_ETH0_MAC_CLK
+#define HI3798MV200_GMACIF_CLK HISTB_ETH0_MACIF_CLK
+#define HI3798MV200_FEMAC_CLK HISTB_ETH1_MAC_CLK
+#define HI3798MV200_FEMACIF_CLK HISTB_ETH1_MACIF_CLK
+#define HI3798MV200_FEPHY_CLK HISTB_ETH1_PHY_CLK
/* clocks provided by mcu CRG */
#define HISTB_MCE_CLK 1