| Message ID | 20240329205904.25002-2-ddrokosov@salutedevices.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | clk: meson: introduce Amlogic A1 SoC Family CPU clock controller driver | expand |
On Fri, Mar 29, 2024 at 11:58:41PM +0300, Dmitry Rokosov wrote: > The 'syspll' PLL is a general-purpose PLL designed specifically for the > CPU clock. It is capable of producing output frequencies within the > range of 768MHz to 1536MHz. > > Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> > --- > .../devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml | 7 +++++-- > include/dt-bindings/clock/amlogic,a1-pll-clkc.h | 2 ++ > 2 files changed, 7 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml > index a59b188a8bf5..fbba57031278 100644 > --- a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml > +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml > @@ -26,11 +26,13 @@ properties: > items: > - description: input fixpll_in > - description: input hifipll_in > + - description: input syspll_in > > clock-names: > items: > - const: fixpll_in > - const: hifipll_in > + - const: syspll_in A new required entry is an ABI break. Please state why that's ok or make it optional (minItems: 2).
Hello Rob, On Mon, Apr 01, 2024 at 09:20:11AM -0500, Rob Herring wrote: > On Fri, Mar 29, 2024 at 11:58:41PM +0300, Dmitry Rokosov wrote: > > The 'syspll' PLL is a general-purpose PLL designed specifically for the > > CPU clock. It is capable of producing output frequencies within the > > range of 768MHz to 1536MHz. > > > > Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> > > --- > > .../devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml | 7 +++++-- > > include/dt-bindings/clock/amlogic,a1-pll-clkc.h | 2 ++ > > 2 files changed, 7 insertions(+), 2 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml > > index a59b188a8bf5..fbba57031278 100644 > > --- a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml > > +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml > > @@ -26,11 +26,13 @@ properties: > > items: > > - description: input fixpll_in > > - description: input hifipll_in > > + - description: input syspll_in > > > > clock-names: > > items: > > - const: fixpll_in > > - const: hifipll_in > > + - const: syspll_in > > A new required entry is an ABI break. Please state why that's ok or make > it optional (minItems: 2). Unfortunatelly, it cannot be optional. I've explained here why: https://lore.kernel.org/all/20240401171933.bqmjsuanqsjvjosn@CAB-WSD-L081021/ """ The clock source sys_pll_div16, being one of the GEN clock parents, plays a crucial role and cannot be tagged as "optional". Unfortunately, it was not implemented earlier due to the cpu clock ctrl driver's pending status on the TODO list. """ Could you please provide guidance on whether there is any alternative approach that could potentially make it possible?
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml index a59b188a8bf5..fbba57031278 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml @@ -26,11 +26,13 @@ properties: items: - description: input fixpll_in - description: input hifipll_in + - description: input syspll_in clock-names: items: - const: fixpll_in - const: hifipll_in + - const: syspll_in required: - compatible @@ -53,7 +55,8 @@ examples: reg = <0 0x7c80 0 0x18c>; #clock-cells = <1>; clocks = <&clkc_periphs CLKID_FIXPLL_IN>, - <&clkc_periphs CLKID_HIFIPLL_IN>; - clock-names = "fixpll_in", "hifipll_in"; + <&clkc_periphs CLKID_HIFIPLL_IN>, + <&clkc_periphs CLKID_SYSPLL_IN>; + clock-names = "fixpll_in", "hifipll_in", "syspll_in"; }; }; diff --git a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h index 2b660c0f2c9f..a702d610589c 100644 --- a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h +++ b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h @@ -21,5 +21,7 @@ #define CLKID_FCLK_DIV5 8 #define CLKID_FCLK_DIV7 9 #define CLKID_HIFI_PLL 10 +#define CLKID_SYS_PLL 11 +#define CLKID_SYS_PLL_DIV16 12 #endif /* __A1_PLL_CLKC_H */
The 'syspll' PLL is a general-purpose PLL designed specifically for the CPU clock. It is capable of producing output frequencies within the range of 768MHz to 1536MHz. Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> --- .../devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml | 7 +++++-- include/dt-bindings/clock/amlogic,a1-pll-clkc.h | 2 ++ 2 files changed, 7 insertions(+), 2 deletions(-)