| Message ID | 20240404122559.898930-7-peter.griffin@linaro.org (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | HSI2, UFS & UFS phy support for Tensor GS101 | expand |
Hi Pete, On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote: > This has some configuration bits such as sharability that > are required by UFS. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- > arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > index 38ac4fb1397e..608369cec47b 100644 > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > @@ -1265,6 +1265,12 @@ cmu_hsi2: clock-controller@14400000 { > clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card"; > }; > > + sysreg_hsi2: syscon@14420000 { > + compatible = "google,gs101-hsi2-sysreg", "syscon"; > + reg = <0x14420000 0x1000>; Should the length not be 0x10000? Cheers, Andre'
Hi André, Thanks for the review. On Fri, 5 Apr 2024 at 08:33, André Draszik <andre.draszik@linaro.org> wrote: > > Hi Pete, > > On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote: > > This has some configuration bits such as sharability that > > are required by UFS. > > > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > > --- > > arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > > index 38ac4fb1397e..608369cec47b 100644 > > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi > > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > > @@ -1265,6 +1265,12 @@ cmu_hsi2: clock-controller@14400000 { > > clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card"; > > }; > > > > + sysreg_hsi2: syscon@14420000 { > > + compatible = "google,gs101-hsi2-sysreg", "syscon"; > > + reg = <0x14420000 0x1000>; > > Should the length not be 0x10000? The downstream kernel uses a length of 0x1000 for all the foobar-sysreg nodes, but checking the specs it does indeed seem that the length should be 0x10000 (and that is what we've used for all the other sysreg nodes upstream). Will update this in v2. regards, Pete
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 38ac4fb1397e..608369cec47b 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1265,6 +1265,12 @@ cmu_hsi2: clock-controller@14400000 { clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card"; }; + sysreg_hsi2: syscon@14420000 { + compatible = "google,gs101-hsi2-sysreg", "syscon"; + reg = <0x14420000 0x1000>; + clocks = <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; + }; + pinctrl_hsi2: pinctrl@14440000 { compatible = "google,gs101-pinctrl"; reg = <0x14440000 0x00001000>;
This has some configuration bits such as sharability that are required by UFS. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)