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Fri, 19 Apr 2024 16:00:27 +0300 From: Jan Dakinevich To: Jan Dakinevich , Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Martin Blumenstingl , Philipp Zabel , Jiucheng Xu , , , , , Subject: [RFC PATCH v3 2/6] clk: meson: axg: share the set of audio helper macro Date: Fri, 19 Apr 2024 15:58:08 +0300 Message-ID: <20240419125812.983409-3-jan.dakinevich@salutedevices.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240419125812.983409-1-jan.dakinevich@salutedevices.com> References: <20240419125812.983409-1-jan.dakinevich@salutedevices.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: p-i-exch-sc-m01.sberdevices.ru (172.16.192.107) To p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 184806 [Apr 19 2024] X-KSMG-AntiSpam-Version: 6.1.0.4 X-KSMG-AntiSpam-Envelope-From: YVDakinevich@sberdevices.ru X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 18 0.3.18 b9d6ada76958f07c6a68617a7ac8df800bc4166c, {Tracking_smtp_not_equal_from}, 100.64.160.123:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;salutedevices.com:7.1.1;127.0.0.199:7.1.2;sberdevices.ru:5.0.1,7.1.1;smtp.sberdevices.ru:5.0.1,7.1.1, FromAlignment: n, {Tracking_smtp_domain_mismatch}, {Tracking_smtp_domain_2level_mismatch}, {Tracking_sender_alignment_int}, {Tracking_white_helo}, ApMailHostAddress: 100.64.160.123 X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/04/18 23:49:00 #24865988 X-KSMG-AntiVirus-Status: Clean, skipped These macro will be used in upcoming audio clock controller for Meson A1 SoC. Signed-off-by: Jan Dakinevich --- drivers/clk/meson/axg-audio.c | 138 +----------------------------- drivers/clk/meson/meson-audio.h | 143 ++++++++++++++++++++++++++++++++ 2 files changed, 144 insertions(+), 137 deletions(-) create mode 100644 drivers/clk/meson/meson-audio.h diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c index 9cd6b5c3aa7e..ee0698bf4383 100644 --- a/drivers/clk/meson/axg-audio.c +++ b/drivers/clk/meson/axg-audio.c @@ -17,6 +17,7 @@ #include #include "meson-clkc-utils.h" +#include "meson-audio.h" #include "axg-audio.h" #include "clk-regmap.h" #include "clk-phase.h" @@ -24,52 +25,6 @@ #include -#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ - .data = &(struct clk_regmap_gate_data){ \ - .offset = (_reg), \ - .bit_idx = (_bit), \ - }, \ - .hw.init = &(struct clk_init_data) { \ - .name = "aud_"#_name, \ - .ops = &clk_regmap_gate_ops, \ - .parent_names = (const char *[]){ #_pname }, \ - .num_parents = 1, \ - .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \ - }, \ -} - -#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \ - .data = &(struct clk_regmap_mux_data){ \ - .offset = (_reg), \ - .mask = (_mask), \ - .shift = (_shift), \ - .flags = (_dflags), \ - }, \ - .hw.init = &(struct clk_init_data){ \ - .name = "aud_"#_name, \ - .ops = &clk_regmap_mux_ops, \ - .parent_data = _pdata, \ - .num_parents = ARRAY_SIZE(_pdata), \ - .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \ - }, \ -} - -#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \ - .data = &(struct clk_regmap_div_data){ \ - .offset = (_reg), \ - .shift = (_shift), \ - .width = (_width), \ - .flags = (_dflags), \ - }, \ - .hw.init = &(struct clk_init_data){ \ - .name = "aud_"#_name, \ - .ops = &clk_regmap_divider_ops, \ - .parent_names = (const char *[]){ #_pname }, \ - .num_parents = 1, \ - .flags = (_iflags), \ - }, \ -} - #define AUD_PCLK_GATE(_name, _reg, _bit) { \ .data = &(struct clk_regmap_gate_data){ \ .offset = (_reg), \ @@ -83,97 +38,6 @@ }, \ } -#define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \ - _hi_shift, _hi_width, _pname, _iflags) { \ - .data = &(struct meson_sclk_div_data) { \ - .div = { \ - .reg_off = (_reg), \ - .shift = (_div_shift), \ - .width = (_div_width), \ - }, \ - .hi = { \ - .reg_off = (_reg), \ - .shift = (_hi_shift), \ - .width = (_hi_width), \ - }, \ - }, \ - .hw.init = &(struct clk_init_data) { \ - .name = "aud_"#_name, \ - .ops = &meson_sclk_div_ops, \ - .parent_names = (const char *[]){ #_pname }, \ - .num_parents = 1, \ - .flags = (_iflags), \ - }, \ -} - -#define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \ - _pname, _iflags) { \ - .data = &(struct meson_clk_triphase_data) { \ - .ph0 = { \ - .reg_off = (_reg), \ - .shift = (_shift0), \ - .width = (_width), \ - }, \ - .ph1 = { \ - .reg_off = (_reg), \ - .shift = (_shift1), \ - .width = (_width), \ - }, \ - .ph2 = { \ - .reg_off = (_reg), \ - .shift = (_shift2), \ - .width = (_width), \ - }, \ - }, \ - .hw.init = &(struct clk_init_data) { \ - .name = "aud_"#_name, \ - .ops = &meson_clk_triphase_ops, \ - .parent_names = (const char *[]){ #_pname }, \ - .num_parents = 1, \ - .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \ - }, \ -} - -#define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) { \ - .data = &(struct meson_clk_phase_data) { \ - .ph = { \ - .reg_off = (_reg), \ - .shift = (_shift), \ - .width = (_width), \ - }, \ - }, \ - .hw.init = &(struct clk_init_data) { \ - .name = "aud_"#_name, \ - .ops = &meson_clk_phase_ops, \ - .parent_names = (const char *[]){ #_pname }, \ - .num_parents = 1, \ - .flags = (_iflags), \ - }, \ -} - -#define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname, \ - _iflags) { \ - .data = &(struct meson_sclk_ws_inv_data) { \ - .ph = { \ - .reg_off = (_reg), \ - .shift = (_shift_ph), \ - .width = (_width), \ - }, \ - .ws = { \ - .reg_off = (_reg), \ - .shift = (_shift_ws), \ - .width = (_width), \ - }, \ - }, \ - .hw.init = &(struct clk_init_data) { \ - .name = "aud_"#_name, \ - .ops = &meson_clk_phase_ops, \ - .parent_names = (const char *[]){ #_pname }, \ - .num_parents = 1, \ - .flags = (_iflags), \ - }, \ -} - /* Audio Master Clocks */ static const struct clk_parent_data mst_mux_parent_data[] = { { .fw_name = "mst_in0", }, diff --git a/drivers/clk/meson/meson-audio.h b/drivers/clk/meson/meson-audio.h new file mode 100644 index 000000000000..cbcdbd487d4a --- /dev/null +++ b/drivers/clk/meson/meson-audio.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ + +#ifndef __MESON_AUDIO_H__ +#define __MESON_AUDIO_H__ + +#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ + .data = &(struct clk_regmap_gate_data){ \ + .offset = (_reg), \ + .bit_idx = (_bit), \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = "aud_"#_name, \ + .ops = &clk_regmap_gate_ops, \ + .parent_names = (const char *[]){ #_pname }, \ + .num_parents = 1, \ + .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \ + }, \ +} + +#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \ + .data = &(struct clk_regmap_mux_data){ \ + .offset = (_reg), \ + .mask = (_mask), \ + .shift = (_shift), \ + .flags = (_dflags), \ + }, \ + .hw.init = &(struct clk_init_data){ \ + .name = "aud_"#_name, \ + .ops = &clk_regmap_mux_ops, \ + .parent_data = _pdata, \ + .num_parents = ARRAY_SIZE(_pdata), \ + .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \ + }, \ +} + +#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \ + .data = &(struct clk_regmap_div_data){ \ + .offset = (_reg), \ + .shift = (_shift), \ + .width = (_width), \ + .flags = (_dflags), \ + }, \ + .hw.init = &(struct clk_init_data){ \ + .name = "aud_"#_name, \ + .ops = &clk_regmap_divider_ops, \ + .parent_names = (const char *[]){ #_pname }, \ + .num_parents = 1, \ + .flags = (_iflags), \ + }, \ +} + +#define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \ + _hi_shift, _hi_width, _pname, _iflags) { \ + .data = &(struct meson_sclk_div_data) { \ + .div = { \ + .reg_off = (_reg), \ + .shift = (_div_shift), \ + .width = (_div_width), \ + }, \ + .hi = { \ + .reg_off = (_reg), \ + .shift = (_hi_shift), \ + .width = (_hi_width), \ + }, \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = "aud_"#_name, \ + .ops = &meson_sclk_div_ops, \ + .parent_names = (const char *[]){ #_pname }, \ + .num_parents = 1, \ + .flags = (_iflags), \ + }, \ +} + +#define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \ + _pname, _iflags) { \ + .data = &(struct meson_clk_triphase_data) { \ + .ph0 = { \ + .reg_off = (_reg), \ + .shift = (_shift0), \ + .width = (_width), \ + }, \ + .ph1 = { \ + .reg_off = (_reg), \ + .shift = (_shift1), \ + .width = (_width), \ + }, \ + .ph2 = { \ + .reg_off = (_reg), \ + .shift = (_shift2), \ + .width = (_width), \ + }, \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = "aud_"#_name, \ + .ops = &meson_clk_triphase_ops, \ + .parent_names = (const char *[]){ #_pname }, \ + .num_parents = 1, \ + .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \ + }, \ +} + +#define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) { \ + .data = &(struct meson_clk_phase_data) { \ + .ph = { \ + .reg_off = (_reg), \ + .shift = (_shift), \ + .width = (_width), \ + }, \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = "aud_"#_name, \ + .ops = &meson_clk_phase_ops, \ + .parent_names = (const char *[]){ #_pname }, \ + .num_parents = 1, \ + .flags = (_iflags), \ + }, \ +} + +#define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname, \ + _iflags) { \ + .data = &(struct meson_sclk_ws_inv_data) { \ + .ph = { \ + .reg_off = (_reg), \ + .shift = (_shift_ph), \ + .width = (_width), \ + }, \ + .ws = { \ + .reg_off = (_reg), \ + .shift = (_shift_ws), \ + .width = (_width), \ + }, \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = "aud_"#_name, \ + .ops = &meson_clk_phase_ops, \ + .parent_names = (const char *[]){ #_pname }, \ + .num_parents = 1, \ + .flags = (_iflags), \ + }, \ +} + +#endif /* __MESON_AUDIO_H__ */