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AJvYcCWzsxTjCJzBwgU64wpYUHF2A2+LptBboNFrAyNzuutnguRjucfvCI1ZZve7wRLkXMtXqoYKmuYsdLi6Zhl2OU4BlAc9rbRz71F+TeM8fvysCO8PguJnBXT0Zs+HuO/micdrp4nkSL/B7PUk+Dx39D/H66b2P6NCcWm/j4u14xs4LO+LSg== X-Gm-Message-State: AOJu0YwGUnTK4eTCCt+TW8GZyhklZPZnSGWcTo9YymtPZoETz8vx+kff vuZpQAPYxBEi3odyXd9fhZFKTBsa4pROCe0X52OfSyddGgj69ZcK5arO X-Google-Smtp-Source: AGHT+IH0d83c7xTax7fuIOWVQkoiDle9wGyhCdq0/Z1yJWMYOpdTGsFWFrlzxl7C3Qi6XsSYe60iZA== X-Received: by 2002:a17:906:fa9a:b0:a55:5520:f43f with SMTP id a640c23a62f3a-a59e4cea3e4mr46264666b.10.1715024641987; Mon, 06 May 2024 12:44:01 -0700 (PDT) Received: from U4.lan ([2a02:810b:f40:4600:1c62:e77:6753:5729]) by smtp.gmail.com with ESMTPSA id f13-20020a1709067f8d00b00a59d146f034sm1367321ejr.132.2024.05.06.12.44.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 May 2024 12:44:01 -0700 (PDT) From: Alex Bee To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Alex Bee Subject: [PATCH 5/7] drm/rockchip: dsi: Add support for RK3128 Date: Mon, 6 May 2024 21:43:40 +0200 Message-ID: <20240506194343.282119-6-knaerzche@gmail.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240506194343.282119-1-knaerzche@gmail.com> References: <20240506194343.282119-1-knaerzche@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The DesignWare MIPI DSI controller found RK3128 SoCs supports up to 4 dsi data lanes. Similar to PX30/RK356x/RV1126 it uses an external DPHY. Signed-off-by: Alex Bee --- .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c index 4cc8ed8f4fbd..58a44af0e9ad 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -153,6 +153,11 @@ #define PX30_DSI_TURNDISABLE BIT(5) #define PX30_DSI_LCDC_SEL BIT(0) +#define RK3128_GRF_LVDS_CON0 0x0150 +#define RK3128_DSI_FORCETXSTOPMODE GENMASK(13, 10) +#define RK3128_DSI_FORCERXMODE BIT(9) +#define RK3128_DSI_TURNDISABLE BIT(8) + #define RK3288_GRF_SOC_CON6 0x025c #define RK3288_DSI0_LCDC_SEL BIT(6) #define RK3288_DSI1_LCDC_SEL BIT(9) @@ -1493,6 +1498,18 @@ static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = { { /* sentinel */ } }; +static const struct rockchip_dw_dsi_chip_data rk3128_chip_data[] = { + { + .reg = 0x10110000, + .lanecfg1_grf_reg = RK3128_GRF_LVDS_CON0, + .lanecfg1 = HIWORD_UPDATE(0, RK3128_DSI_TURNDISABLE | + RK3128_DSI_FORCERXMODE | + RK3128_DSI_FORCETXSTOPMODE), + .max_data_lanes = 4, + }, + { /* sentinel */ } +}; + static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = { { .reg = 0xff960000, @@ -1670,6 +1687,9 @@ static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { { .compatible = "rockchip,px30-mipi-dsi", .data = &px30_chip_data, + }, { + .compatible = "rockchip,rk3128-mipi-dsi", + .data = &rk3128_chip_data, }, { .compatible = "rockchip,rk3288-mipi-dsi", .data = &rk3288_chip_data,