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AJvYcCXZuXVwFkoROKWwUb+XV80JQMOfIxbH+5W2yz/06wck+cZNRGGoz9PVQSVdBu45Kgstk+YijdMz0rDOExacqGG2S2mTrNJQHuI6DjSaRMAP6J/gcHJ5GP0I2C1A24EgG+VK2kXTT80+JIRmO8npgT9IMql0bbICZWu5jQOk9X5Joh4afQ== X-Gm-Message-State: AOJu0Yz+qfekPvW+t6tFHWa6ZEM7EZsKlA/grW3ekJgBKCFcomJrFewH vP44w8FyigtR5pV41CUmuOok2iRrQjZI3BPdwOTYAJH1chQPlHg= X-Google-Smtp-Source: AGHT+IHh+dso5MhBn431TAWM/uD/cNhYOwNyyWPRjGSzNSz1xBMrETqF5hbahKDBfppAyPHSKftcWQ== X-Received: by 2002:a05:6512:40a:b0:51c:c1a3:a4f9 with SMTP id 2adb3069b0e04-5217cd48861mr3707317e87.64.1715263624613; Thu, 09 May 2024 07:07:04 -0700 (PDT) Received: from U4.lan ([2a02:810b:f40:4600:b44:d8c3:6fa8:c46f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502baad058sm1793311f8f.66.2024.05.09.07.07.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 07:07:03 -0700 (PDT) From: Alex Bee To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Alex Bee Subject: [PATCH v3 6/7] ARM: dts: rockchip: Add D-PHY for RK3128 Date: Thu, 9 May 2024 16:06:52 +0200 Message-ID: <20240509140653.168591-7-knaerzche@gmail.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240509140653.168591-1-knaerzche@gmail.com> References: <20240509140653.168591-1-knaerzche@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The InnoSilicon D-PHY found in RK3128 SoCs supports DSI/LVDS/TTL with a maximum transfer rate of 1 Gbps per lane. While adding it, also add it's clocks to RK3128_PD_VIO powerdomain as the phy is part of it. Signed-off-by: Alex Bee --- changes since v1: - also added SCLK_MIPI_24M to powerdomain - reword commit message arch/arm/boot/dts/rockchip/rk3128.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index fb98873fd94e..fbd95bb08cd3 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -216,6 +216,8 @@ power-domain@RK3128_PD_VIO { <&cru ACLK_LCDC0>, <&cru HCLK_LCDC0>, <&cru PCLK_MIPI>, + <&cru PCLK_MIPIPHY>, + <&cru SCLK_MIPI_24M>, <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru ACLK_VIO0>, @@ -496,6 +498,18 @@ hdmi_out: port@1 { }; }; + dphy: phy@20038000 { + compatible = "rockchip,rk3128-dsi-dphy"; + reg = <0x20038000 0x4000>; + clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>; + clock-names = "ref", "pclk"; + resets = <&cru SRST_MIPIPHY_P>; + reset-names = "apb"; + power-domains = <&power RK3128_PD_VIO>; + #phy-cells = <0>; + status = "disabled"; + }; + timer0: timer@20044000 { compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; reg = <0x20044000 0x20>;