| Message ID | 20240530083513.4135052-2-wenst@chromium.org (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | powervr: MT8173 GPU support | expand |
On Thu, May 30, 2024 at 04:35:00PM +0800, Chen-Yu Tsai wrote: > The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP > in the datasheet, that contains clock gates, some power sequence signal > delays, and other unknown registers that get toggled when the GPU is > powered on. > > The clock gates are exposed as clocks provided by a clock controller, > while the power sequencing bits are exposed as one singular power domain. > > Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> > --- > .../clock/mediatek,mt8173-mfgtop.yaml | 71 +++++++++++++++++++ > include/dt-bindings/clock/mt8173-clk.h | 7 ++ > 2 files changed, 78 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml > > diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml > new file mode 100644 > index 000000000000..03c3c1f8cf75 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml > @@ -0,0 +1,71 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > + > +$id: http://devicetree.org/schemas/clock/mediatek,mt8173-mfgtop.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek MT8173 MFG TOP controller > + > +maintainers: > + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > + > +description: > + The MFG TOP glue layer controls various signals going to the MFG (GPU) > + block on the MT8173. > + > +properties: > + compatible: > + const: mediatek,mt8173-mfgtop > + > + reg: > + maxItems: 1 > + > + clocks: > + minItems: 4 minItems is not needed when minItems == maxItems. > + maxItems: 4 > + > + clock-names: > + items: > + - const: sys > + - const: mem > + - const: core > + - const: clk26m > + > + power-domains: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > + '#power-domain-cells': > + const: 0 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - power-domains > + - '#clock-cells' > + - '#power-domain-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/mt8173-clk.h> > + #include <dt-bindings/power/mt8173-power.h> > + > + mfgtop: clock-controller@13fff000 { The label here is used, so drop it. Otherwise, Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor.
On Thu, May 30, 2024 at 11:43 PM Conor Dooley <conor@kernel.org> wrote: > > On Thu, May 30, 2024 at 04:35:00PM +0800, Chen-Yu Tsai wrote: > > The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP > > in the datasheet, that contains clock gates, some power sequence signal > > delays, and other unknown registers that get toggled when the GPU is > > powered on. > > > > The clock gates are exposed as clocks provided by a clock controller, > > while the power sequencing bits are exposed as one singular power domain. > > > > Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> > > --- > > .../clock/mediatek,mt8173-mfgtop.yaml | 71 +++++++++++++++++++ > > include/dt-bindings/clock/mt8173-clk.h | 7 ++ > > 2 files changed, 78 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml > > > > diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml > > new file mode 100644 > > index 000000000000..03c3c1f8cf75 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml > > @@ -0,0 +1,71 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > + > > +$id: http://devicetree.org/schemas/clock/mediatek,mt8173-mfgtop.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MediaTek MT8173 MFG TOP controller > > + > > +maintainers: > > + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > > + > > +description: > > + The MFG TOP glue layer controls various signals going to the MFG (GPU) > > + block on the MT8173. > > + > > +properties: > > + compatible: > > + const: mediatek,mt8173-mfgtop > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + minItems: 4 > > minItems is not needed when minItems == maxItems. Ack. > > + maxItems: 4 > > + > > + clock-names: > > + items: > > + - const: sys > > + - const: mem > > + - const: core > > + - const: clk26m > > + > > + power-domains: > > + maxItems: 1 > > + > > + '#clock-cells': > > + const: 1 > > + > > + '#power-domain-cells': > > + const: 0 > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - clock-names > > + - power-domains > > + - '#clock-cells' > > + - '#power-domain-cells' > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/mt8173-clk.h> > > + #include <dt-bindings/power/mt8173-power.h> > > + > > + mfgtop: clock-controller@13fff000 { > > The label here is used, so drop it. Assume you mean _not_ used. Dropping. :D > Otherwise, > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks!
On Fri, May 31, 2024 at 03:29:06PM +0800, Chen-Yu Tsai wrote: > On Thu, May 30, 2024 at 11:43 PM Conor Dooley <conor@kernel.org> wrote: > > > > On Thu, May 30, 2024 at 04:35:00PM +0800, Chen-Yu Tsai wrote: > > > + #include <dt-bindings/clock/mt8173-clk.h> > > > + #include <dt-bindings/power/mt8173-power.h> > > > + > > > + mfgtop: clock-controller@13fff000 { > > > > The label here is used, so drop it. > > Assume you mean _not_ used. Dropping. :D Correct :D
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml new file mode 100644 index 000000000000..03c3c1f8cf75 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/clock/mediatek,mt8173-mfgtop.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8173 MFG TOP controller + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + +description: + The MFG TOP glue layer controls various signals going to the MFG (GPU) + block on the MT8173. + +properties: + compatible: + const: mediatek,mt8173-mfgtop + + reg: + maxItems: 1 + + clocks: + minItems: 4 + maxItems: 4 + + clock-names: + items: + - const: sys + - const: mem + - const: core + - const: clk26m + + power-domains: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8173-clk.h> + #include <dt-bindings/power/mt8173-power.h> + + mfgtop: clock-controller@13fff000 { + compatible = "mediatek,mt8173-mfgtop"; + reg = <0x13fff000 0x1000>; + clocks = <&topckgen CLK_TOP_AXI_MFG_IN_SEL>, + <&topckgen CLK_TOP_MEM_MFG_IN_SEL>, + <&topckgen CLK_TOP_MFG_SEL>, + <&clk26m>; + clock-names = "sys", "mem", "core", "clk26m"; + power-domains = <&spm MT8173_POWER_DOMAIN_MFG>; + #clock-cells = <1>; + #power-domain-cells = <0>; + }; diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h index 3d00c98b9654..89e982f771db 100644 --- a/include/dt-bindings/clock/mt8173-clk.h +++ b/include/dt-bindings/clock/mt8173-clk.h @@ -243,6 +243,13 @@ #define CLK_IMG_FD 7 #define CLK_IMG_NR_CLK 8 +/* MFG_SYS */ + +#define CLK_MFG_AXI 0 +#define CLK_MFG_MEM 1 +#define CLK_MFG_G3D 2 +#define CLK_MFG_26M 3 + /* MM_SYS */ #define CLK_MM_SMI_COMMON 1
The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP in the datasheet, that contains clock gates, some power sequence signal delays, and other unknown registers that get toggled when the GPU is powered on. The clock gates are exposed as clocks provided by a clock controller, while the power sequencing bits are exposed as one singular power domain. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> --- .../clock/mediatek,mt8173-mfgtop.yaml | 71 +++++++++++++++++++ include/dt-bindings/clock/mt8173-clk.h | 7 ++ 2 files changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml