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AJvYcCWI3679cgJ5HuIR9a4txl09k5mGFQLGZR8rsID49RyZv72xnNuL9M+HVAJpUNrMcZ2XuxZ81TTpxt1V6CL2H2+wKX0nE1scWXEp X-Gm-Message-State: AOJu0YyO2SPPEKTJoidrPYTTgR1/ZWePkIt57wuGYiTZoumVdIOTtYdF QqE1SM3p0yrGyT+qBuAZaibnCfGPytJPUb/BXjKzneouH6nGf0iZe459jsPYkg== X-Google-Smtp-Source: AGHT+IFpzoyjS8oEHpsPco6/0czovfTG+BgxZDwOvkJUGlKruUTXsaiUOVp8Alhb12YxLjpScrPXfA== X-Received: by 2002:a17:902:74c8:b0:1f4:7f18:6d7c with SMTP id d9443c01a7336-1f61a4db927mr16665575ad.61.1717058137709; Thu, 30 May 2024 01:35:37 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:65f0:63a9:90bb:50b8]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f617390fe7sm10950635ad.146.2024.05.30.01.35.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 May 2024 01:35:37 -0700 (PDT) From: Chen-Yu Tsai To: Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: Chen-Yu Tsai , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/6] arm64: dts: mediatek: mt8173: Fix MFG_ASYNC power domain clock Date: Thu, 30 May 2024 16:35:04 +0800 Message-ID: <20240530083513.4135052-6-wenst@chromium.org> X-Mailer: git-send-email 2.45.1.288.g0e0cd299f1-goog In-Reply-To: <20240530083513.4135052-1-wenst@chromium.org> References: <20240530083513.4135052-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The MFG_ASYNC domain, which is likely associated to the whole MFG block, currently specifies clk26m as its domain clock. This is bogus, since the clock is an external crystal with no controls. Also, the MFG block has a independent CLK_TOP_AXI_MFG_IN_SEL clock, which according to the block diagram, gates access to the hardware registers. Having this one as the domain clock makes much more sense. This also fixes access to the MFGTOP registers. Change the MFG_ASYNC domain clock to CLK_TOP_AXI_MFG_IN_SEL. Fixes: 8b6562644df9 ("arm64: dts: mediatek: Add mt8173 power domain controller") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 3458be7f7f61..136b28f80cc2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -497,7 +497,7 @@ power-domain@MT8173_POWER_DOMAIN_USB { }; mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC { reg = ; - clocks = <&clk26m>; + clocks = <&topckgen CLK_TOP_AXI_MFG_IN_SEL>; clock-names = "mfg"; #address-cells = <1>; #size-cells = <0>;