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AJvYcCV0VOL6d8dkN11I2hnVFbsU/PBZ6y4L72X9VrB9Cw8od/+qdmIiWAzOlslAEZp9GxORbMexCWIabppbLu/+jHp4viev2YvuISgu X-Gm-Message-State: AOJu0YxQ8mJ1Ln57D4r5fXdWQ7MYEQNhUaehVt3ClX9a7rtUUJdadJnb paynlYEL8XI8TRX9CkVby+Ge0aAUXAH+lvDpJJKkvsQFwcK6Yxiol421pmXPFw== X-Google-Smtp-Source: AGHT+IFl9n7DktKEcpEJ4WGQz7AcjFouxFiRzMPk6dDKBcDqPpXqbxbt5Utw0hXKMF4XUXofIeg46w== X-Received: by 2002:a05:6a21:99a3:b0:1b1:ec17:e59c with SMTP id adf61e73a8af0-1b264618a95mr1679425637.61.1717058141165; Thu, 30 May 2024 01:35:41 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:65f0:63a9:90bb:50b8]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f617390fe7sm10950635ad.146.2024.05.30.01.35.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 May 2024 01:35:40 -0700 (PDT) From: Chen-Yu Tsai To: Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: Chen-Yu Tsai , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/6] arm64: dts: mediatek: mt8173: Add GPU device nodes Date: Thu, 30 May 2024 16:35:05 +0800 Message-ID: <20240530083513.4135052-7-wenst@chromium.org> X-Mailer: git-send-email 2.45.1.288.g0e0cd299f1-goog In-Reply-To: <20240530083513.4135052-1-wenst@chromium.org> References: <20240530083513.4135052-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is part of the Series6XT, another variation of the Rogue family of GPUs. On top of the GPU is a glue layer that handles some clock and power signals. Add device nodes for both. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 136b28f80cc2..3d7b9cc20a16 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -993,6 +993,30 @@ u2port1: usb-phy@11291000 { }; }; + gpu: gpu@13000000 { + compatible = "mediatek,mt8173-gpu", "img,powervr-6xt"; + reg = <0 0x13000000 0 0x10000>; + interrupts = ; + clocks = <&mfgtop CLK_MFG_G3D>, + <&mfgtop CLK_MFG_MEM>, + <&mfgtop CLK_MFG_AXI>; + clock-names = "core", "mem", "sys"; + power-domains = <&mfgtop>; + }; + + mfgtop: clock-controller@13fff000 { + compatible = "mediatek,mt8173-mfgtop"; + reg = <0 0x13fff000 0 0x1000>; + clocks = <&topckgen CLK_TOP_AXI_MFG_IN_SEL>, + <&topckgen CLK_TOP_MEM_MFG_IN_SEL>, + <&topckgen CLK_TOP_MFG_SEL>, + <&clk26m>; + clock-names = "sys", "mem", "core", "clk26m"; + power-domains = <&spm MT8173_POWER_DOMAIN_MFG>; + #clock-cells = <1>; + #power-domain-cells = <0>; + }; + mmsys: syscon@14000000 { compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>;