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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Use the same clk clocks ops as the dptx0_aux_clk_src, dptx2_aux_clk_src and dptx3_aux_clk_src. Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver") Signed-off-by: Neil Armstrong --- drivers/clk/qcom/dispcc-sm8650.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8650.c index 31c82f791b44..70944b7128e2 100644 --- a/drivers/clk/qcom/dispcc-sm8650.c +++ b/drivers/clk/qcom/dispcc-sm8650.c @@ -398,7 +398,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { .parent_data = disp_cc_parent_data_0, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_dp_ops, + .ops = &clk_rcg2_shared_ops, }, };