diff mbox series

[v3,2/2] clk: renesas: r9a09g057-cpg: Add clock and reset entries for GTM/RIIC/SDHI/WDT

Message ID 20240828093822.162855-3-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State Awaiting Upstream, archived
Headers show
Series clk: renesas: rzv2h-cpg: Add divider clock support | expand

Commit Message

Lad, Prabhakar Aug. 28, 2024, 9:38 a.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add clock and reset entries for GTM, RIIC, SDHI and WDT IP blocks.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2->v3
- Moved DDIV_PACK() macro to patch #1

v1->v2
- Updated DDIV_PACK macro to accommodate width 
---
 drivers/clk/renesas/r9a09g057-cpg.c | 84 +++++++++++++++++++++++++++++
 drivers/clk/renesas/rzv2h-cpg.h     |  4 ++
 2 files changed, 88 insertions(+)

Comments

Biju Das Aug. 28, 2024, 9:53 a.m. UTC | #1 
Hi Prabhakar,

Thanks for the patch.

> -----Original Message-----
> From: Prabhakar <prabhakar.csengg@gmail.com>
> Sent: Wednesday, August 28, 2024 10:38 AM
> Subject: [PATCH v3 2/2] clk: renesas: r9a09g057-cpg: Add clock and reset entries for GTM/RIIC/SDHI/WDT
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Add clock and reset entries for GTM, RIIC, SDHI and WDT IP blocks.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3
> - Moved DDIV_PACK() macro to patch #1
> 
> v1->v2
> - Updated DDIV_PACK macro to accommodate width
> ---
>  drivers/clk/renesas/r9a09g057-cpg.c | 84 +++++++++++++++++++++++++++++
>  drivers/clk/renesas/rzv2h-cpg.h     |  4 ++
>  2 files changed, 88 insertions(+)
> 
> diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
> index 9722b810e027..3ee32db5c0af 100644
> --- a/drivers/clk/renesas/r9a09g057-cpg.c
> +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> @@ -25,16 +25,31 @@ enum clk_ids {
> 
>  	/* PLL Clocks */
>  	CLK_PLLCM33,
> +	CLK_PLLCLN,
>  	CLK_PLLDTY,
>  	CLK_PLLCA55,
> 
>  	/* Internal Core Clocks */
>  	CLK_PLLCM33_DIV16,
> +	CLK_PLLCLN_DIV2,
> +	CLK_PLLCLN_DIV8,
> +	CLK_PLLCLN_DIV16,
> +	CLK_PLLDTY_ACPU,
> +	CLK_PLLDTY_ACPU_DIV4,
> 
>  	/* Module Clocks */
>  	MOD_CLK_BASE,
>  };
> 
> +static const struct clk_div_table dtable_2_64[] = {
> +	{0, 2},
> +	{1, 4},
> +	{2, 8},
> +	{3, 16},
> +	{4, 64},
> +	{0, 0},

Is it ok to have {0, 2} first entry and {0, 0} last entry on the same table?

Cheers,
Biju

> +};
> +
>  static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
>  	/* External Clock Inputs */
>  	DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), @@ -43,23 +58,92 @@ static const struct cpg_core_clk
> r9a09g057_core_clks[] __initconst = {
> 
>  	/* PLL Clocks */
>  	DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
> +	DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
>  	DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
>  	DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
> 
>  	/* Internal Core Clocks */
>  	DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
> 
> +	DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
> +	DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
> +	DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
> +
> +	DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
> +	DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU,
> +1, 4),
> +
>  	/* Core Clocks */
>  	DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
>  	DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),  };
> 
>  static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
> +	DEF_MOD("gtm_0_pclk",			CLK_PLLCM33_DIV16, 4, 3, 2, 3),
> +	DEF_MOD("gtm_1_pclk",			CLK_PLLCM33_DIV16, 4, 4, 2, 4),
> +	DEF_MOD("gtm_2_pclk",			CLK_PLLCLN_DIV16, 4, 5, 2, 5),
> +	DEF_MOD("gtm_3_pclk",			CLK_PLLCLN_DIV16, 4, 6, 2, 6),
> +	DEF_MOD("gtm_4_pclk",			CLK_PLLCLN_DIV16, 4, 7, 2, 7),
> +	DEF_MOD("gtm_5_pclk",			CLK_PLLCLN_DIV16, 4, 8, 2, 8),
> +	DEF_MOD("gtm_6_pclk",			CLK_PLLCLN_DIV16, 4, 9, 2, 9),
> +	DEF_MOD("gtm_7_pclk",			CLK_PLLCLN_DIV16, 4, 10, 2, 10),
> +	DEF_MOD("wdt_0_clkp",			CLK_PLLCM33_DIV16, 4, 11, 2, 11),
> +	DEF_MOD("wdt_0_clk_loco",		CLK_QEXTAL, 4, 12, 2, 12),
> +	DEF_MOD("wdt_1_clkp",			CLK_PLLCLN_DIV16, 4, 13, 2, 13),
> +	DEF_MOD("wdt_1_clk_loco",		CLK_QEXTAL, 4, 14, 2, 14),
> +	DEF_MOD("wdt_2_clkp",			CLK_PLLCLN_DIV16, 4, 15, 2, 15),
> +	DEF_MOD("wdt_2_clk_loco",		CLK_QEXTAL, 5, 0, 2, 16),
> +	DEF_MOD("wdt_3_clkp",			CLK_PLLCLN_DIV16, 5, 1, 2, 17),
> +	DEF_MOD("wdt_3_clk_loco",		CLK_QEXTAL, 5, 2, 2, 18),
>  	DEF_MOD("scif_0_clk_pck",		CLK_PLLCM33_DIV16, 8, 15, 4, 15),
> +	DEF_MOD("riic_8_ckm",			CLK_PLLCM33_DIV16, 9, 3, 4, 19),
> +	DEF_MOD("riic_0_ckm",			CLK_PLLCLN_DIV16, 9, 4, 4, 20),
> +	DEF_MOD("riic_1_ckm",			CLK_PLLCLN_DIV16, 9, 5, 4, 21),
> +	DEF_MOD("riic_2_ckm",			CLK_PLLCLN_DIV16, 9, 6, 4, 22),
> +	DEF_MOD("riic_3_ckm",			CLK_PLLCLN_DIV16, 9, 7, 4, 23),
> +	DEF_MOD("riic_4_ckm",			CLK_PLLCLN_DIV16, 9, 8, 4, 24),
> +	DEF_MOD("riic_5_ckm",			CLK_PLLCLN_DIV16, 9, 9, 4, 25),
> +	DEF_MOD("riic_6_ckm",			CLK_PLLCLN_DIV16, 9, 10, 4, 26),
> +	DEF_MOD("riic_7_ckm",			CLK_PLLCLN_DIV16, 9, 11, 4, 27),
> +	DEF_MOD("sdhi_0_imclk",			CLK_PLLCLN_DIV8, 10, 3, 5, 3),
> +	DEF_MOD("sdhi_0_imclk2",		CLK_PLLCLN_DIV8, 10, 4, 5, 4),
> +	DEF_MOD("sdhi_0_clk_hs",		CLK_PLLCLN_DIV2, 10, 5, 5, 5),
> +	DEF_MOD("sdhi_0_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6),
> +	DEF_MOD("sdhi_1_imclk",			CLK_PLLCLN_DIV8, 10, 7, 5, 7),
> +	DEF_MOD("sdhi_1_imclk2",		CLK_PLLCLN_DIV8, 10, 8, 5, 8),
> +	DEF_MOD("sdhi_1_clk_hs",		CLK_PLLCLN_DIV2, 10, 9, 5, 9),
> +	DEF_MOD("sdhi_1_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10),
> +	DEF_MOD("sdhi_2_imclk",			CLK_PLLCLN_DIV8, 10, 11, 5, 11),
> +	DEF_MOD("sdhi_2_imclk2",		CLK_PLLCLN_DIV8, 10, 12, 5, 12),
> +	DEF_MOD("sdhi_2_clk_hs",		CLK_PLLCLN_DIV2, 10, 13, 5, 13),
> +	DEF_MOD("sdhi_2_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14),
>  };
> 
>  static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
> +	DEF_RST(6, 13, 2, 30),		/* GTM_0_PRESETZ */
> +	DEF_RST(6, 14, 2, 31),		/* GTM_1_PRESETZ */
> +	DEF_RST(6, 15, 3, 0),		/* GTM_2_PRESETZ */
> +	DEF_RST(7, 0, 3, 1),		/* GTM_3_PRESETZ */
> +	DEF_RST(7, 1, 3, 2),		/* GTM_4_PRESETZ */
> +	DEF_RST(7, 2, 3, 3),		/* GTM_5_PRESETZ */
> +	DEF_RST(7, 3, 3, 4),		/* GTM_6_PRESETZ */
> +	DEF_RST(7, 4, 3, 5),		/* GTM_7_PRESETZ */
> +	DEF_RST(7, 5, 3, 6),		/* WDT_0_RESET */
> +	DEF_RST(7, 6, 3, 7),		/* WDT_1_RESET */
> +	DEF_RST(7, 7, 3, 8),		/* WDT_2_RESET */
> +	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */
>  	DEF_RST(9, 5, 4, 6),		/* SCIF_0_RST_SYSTEM_N */
> +	DEF_RST(9, 8, 4, 9),		/* RIIC_0_MRST */
> +	DEF_RST(9, 9, 4, 10),		/* RIIC_1_MRST */
> +	DEF_RST(9, 10, 4, 11),		/* RIIC_2_MRST */
> +	DEF_RST(9, 11, 4, 12),		/* RIIC_3_MRST */
> +	DEF_RST(9, 12, 4, 13),		/* RIIC_4_MRST */
> +	DEF_RST(9, 13, 4, 14),		/* RIIC_5_MRST */
> +	DEF_RST(9, 14, 4, 15),		/* RIIC_6_MRST */
> +	DEF_RST(9, 15, 4, 16),		/* RIIC_7_MRST */
> +	DEF_RST(10, 0, 4, 17),		/* RIIC_8_MRST */
> +	DEF_RST(10, 7, 4, 24),		/* SDHI_0_IXRST */
> +	DEF_RST(10, 8, 4, 25),		/* SDHI_1_IXRST */
> +	DEF_RST(10, 9, 4, 26),		/* SDHI_2_IXRST */
>  };
> 
>  const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = { diff --git
> a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index 1c7a979ab790..1bd406c69015
> 100644
> --- a/drivers/clk/renesas/rzv2h-cpg.h
> +++ b/drivers/clk/renesas/rzv2h-cpg.h
> @@ -31,6 +31,10 @@ struct ddiv {
>  		.monbit = _monbit \
>  	})
> 
> +#define CPG_CDDIV0		(0x400)
> +
> +#define CDDIV0_DIVCTL2	DDIV_PACK(CPG_CDDIV0, 8, 3, 2)
> +
>  /**
>   * Definitions of CPG Core Clocks
>   *
> --
> 2.34.1
Lad, Prabhakar Aug. 28, 2024, 10 a.m. UTC | #2 
Hi Biju,

On Wed, Aug 28, 2024 at 10:53 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> Thanks for the patch.
>
> > -----Original Message-----
> > From: Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: Wednesday, August 28, 2024 10:38 AM
> > Subject: [PATCH v3 2/2] clk: renesas: r9a09g057-cpg: Add clock and reset entries for GTM/RIIC/SDHI/WDT
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add clock and reset entries for GTM, RIIC, SDHI and WDT IP blocks.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v2->v3
> > - Moved DDIV_PACK() macro to patch #1
> >
> > v1->v2
> > - Updated DDIV_PACK macro to accommodate width
> > ---
> >  drivers/clk/renesas/r9a09g057-cpg.c | 84 +++++++++++++++++++++++++++++
> >  drivers/clk/renesas/rzv2h-cpg.h     |  4 ++
> >  2 files changed, 88 insertions(+)
> >
> > diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
> > index 9722b810e027..3ee32db5c0af 100644
> > --- a/drivers/clk/renesas/r9a09g057-cpg.c
> > +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> > @@ -25,16 +25,31 @@ enum clk_ids {
> >
> >       /* PLL Clocks */
> >       CLK_PLLCM33,
> > +     CLK_PLLCLN,
> >       CLK_PLLDTY,
> >       CLK_PLLCA55,
> >
> >       /* Internal Core Clocks */
> >       CLK_PLLCM33_DIV16,
> > +     CLK_PLLCLN_DIV2,
> > +     CLK_PLLCLN_DIV8,
> > +     CLK_PLLCLN_DIV16,
> > +     CLK_PLLDTY_ACPU,
> > +     CLK_PLLDTY_ACPU_DIV4,
> >
> >       /* Module Clocks */
> >       MOD_CLK_BASE,
> >  };
> >
> > +static const struct clk_div_table dtable_2_64[] = {
> > +     {0, 2},
> > +     {1, 4},
> > +     {2, 8},
> > +     {3, 16},
> > +     {4, 64},
> > +     {0, 0},
>
> Is it ok to have {0, 2} first entry and {0, 0} last entry on the same table?
>
You mean is it prohibited to add (I haven't seen issues)?

Cheers,
Prabhakar
Biju Das Aug. 28, 2024, 10:10 a.m. UTC | #3 
> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> Sent: Wednesday, August 28, 2024 11:00 AM
> Subject: Re: [PATCH v3 2/2] clk: renesas: r9a09g057-cpg: Add clock and reset entries for
> GTM/RIIC/SDHI/WDT
> 
> Hi Biju,
> 
> On Wed, Aug 28, 2024 at 10:53 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> >
> > Hi Prabhakar,
> >
> > Thanks for the patch.
> >
> > > -----Original Message-----
> > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > Sent: Wednesday, August 28, 2024 10:38 AM
> > > Subject: [PATCH v3 2/2] clk: renesas: r9a09g057-cpg: Add clock and reset entries for
> GTM/RIIC/SDHI/WDT
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Add clock and reset entries for GTM, RIIC, SDHI and WDT IP blocks.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v2->v3
> > > - Moved DDIV_PACK() macro to patch #1
> > >
> > > v1->v2
> > > - Updated DDIV_PACK macro to accommodate width
> > > ---
> > >  drivers/clk/renesas/r9a09g057-cpg.c | 84 +++++++++++++++++++++++++++++
> > >  drivers/clk/renesas/rzv2h-cpg.h     |  4 ++
> > >  2 files changed, 88 insertions(+)
> > >
> > > diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
> > > index 9722b810e027..3ee32db5c0af 100644
> > > --- a/drivers/clk/renesas/r9a09g057-cpg.c
> > > +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> > > @@ -25,16 +25,31 @@ enum clk_ids {
> > >
> > >       /* PLL Clocks */
> > >       CLK_PLLCM33,
> > > +     CLK_PLLCLN,
> > >       CLK_PLLDTY,
> > >       CLK_PLLCA55,
> > >
> > >       /* Internal Core Clocks */
> > >       CLK_PLLCM33_DIV16,
> > > +     CLK_PLLCLN_DIV2,
> > > +     CLK_PLLCLN_DIV8,
> > > +     CLK_PLLCLN_DIV16,
> > > +     CLK_PLLDTY_ACPU,
> > > +     CLK_PLLDTY_ACPU_DIV4,
> > >
> > >       /* Module Clocks */
> > >       MOD_CLK_BASE,
> > >  };
> > >
> > > +static const struct clk_div_table dtable_2_64[] = {
> > > +     {0, 2},
> > > +     {1, 4},
> > > +     {2, 8},
> > > +     {3, 16},
> > > +     {4, 64},
> > > +     {0, 0},
> >
> > Is it ok to have {0, 2} first entry and {0, 0} last entry on the same table?
> >
> You mean is it prohibited to add (I haven't seen issues)?

2 different divider values{2, 0) for the value 0 in the table. You maybe correct.

Cheers,
Biju
Lad, Prabhakar Aug. 28, 2024, 10:20 a.m. UTC | #4 
On Wed, Aug 28, 2024 at 11:10 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: Wednesday, August 28, 2024 11:00 AM
> > Subject: Re: [PATCH v3 2/2] clk: renesas: r9a09g057-cpg: Add clock and reset entries for
> > GTM/RIIC/SDHI/WDT
> >
> > Hi Biju,
> >
> > On Wed, Aug 28, 2024 at 10:53 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > >
> > > Hi Prabhakar,
> > >
> > > Thanks for the patch.
> > >
> > > > -----Original Message-----
> > > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > > Sent: Wednesday, August 28, 2024 10:38 AM
> > > > Subject: [PATCH v3 2/2] clk: renesas: r9a09g057-cpg: Add clock and reset entries for
> > GTM/RIIC/SDHI/WDT
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Add clock and reset entries for GTM, RIIC, SDHI and WDT IP blocks.
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > v2->v3
> > > > - Moved DDIV_PACK() macro to patch #1
> > > >
> > > > v1->v2
> > > > - Updated DDIV_PACK macro to accommodate width
> > > > ---
> > > >  drivers/clk/renesas/r9a09g057-cpg.c | 84 +++++++++++++++++++++++++++++
> > > >  drivers/clk/renesas/rzv2h-cpg.h     |  4 ++
> > > >  2 files changed, 88 insertions(+)
> > > >
> > > > diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
> > > > index 9722b810e027..3ee32db5c0af 100644
> > > > --- a/drivers/clk/renesas/r9a09g057-cpg.c
> > > > +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> > > > @@ -25,16 +25,31 @@ enum clk_ids {
> > > >
> > > >       /* PLL Clocks */
> > > >       CLK_PLLCM33,
> > > > +     CLK_PLLCLN,
> > > >       CLK_PLLDTY,
> > > >       CLK_PLLCA55,
> > > >
> > > >       /* Internal Core Clocks */
> > > >       CLK_PLLCM33_DIV16,
> > > > +     CLK_PLLCLN_DIV2,
> > > > +     CLK_PLLCLN_DIV8,
> > > > +     CLK_PLLCLN_DIV16,
> > > > +     CLK_PLLDTY_ACPU,
> > > > +     CLK_PLLDTY_ACPU_DIV4,
> > > >
> > > >       /* Module Clocks */
> > > >       MOD_CLK_BASE,
> > > >  };
> > > >
> > > > +static const struct clk_div_table dtable_2_64[] = {
> > > > +     {0, 2},
> > > > +     {1, 4},
> > > > +     {2, 8},
> > > > +     {3, 16},
> > > > +     {4, 64},
> > > > +     {0, 0},
> > >
> > > Is it ok to have {0, 2} first entry and {0, 0} last entry on the same table?
> > >
> > You mean is it prohibited to add (I haven't seen issues)?
>
> 2 different divider values{2, 0) for the value 0 in the table. You maybe correct.
>
AFAIK we add sentinel entry at the end of clk_div_table[], see below

https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/clk/renesas/rcar-gen4-cpg.c?h=next-20240828#n415
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/clk/renesas/r9a07g044-cpg.c?h=next-20240828#n80
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/clk/renesas/rcar-gen2-cpg.c?h=next-20240828#n202
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/clk/renesas/rcar-gen3-cpg.c?h=next-20240828#n327

Cheers,
Prabhakar
Biju Das Aug. 28, 2024, 10:22 a.m. UTC | #5 
> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> Sent: Wednesday, August 28, 2024 11:20 AM
> Subject: Re: [PATCH v3 2/2] clk: renesas: r9a09g057-cpg: Add clock and reset entries for
> GTM/RIIC/SDHI/WDT
> 
> On Wed, Aug 28, 2024 at 11:10 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> >
> >
> >
> > > -----Original Message-----
> > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> > > Sent: Wednesday, August 28, 2024 11:00 AM
> > > Subject: Re: [PATCH v3 2/2] clk: renesas: r9a09g057-cpg: Add clock
> > > and reset entries for GTM/RIIC/SDHI/WDT
> > >
> > > Hi Biju,
> > >
> > > On Wed, Aug 28, 2024 at 10:53 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > >
> > > > Hi Prabhakar,
> > > >
> > > > Thanks for the patch.
> > > >
> > > > > -----Original Message-----
> > > > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > > > Sent: Wednesday, August 28, 2024 10:38 AM
> > > > > Subject: [PATCH v3 2/2] clk: renesas: r9a09g057-cpg: Add clock
> > > > > and reset entries for
> > > GTM/RIIC/SDHI/WDT
> > > > >
> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > >
> > > > > Add clock and reset entries for GTM, RIIC, SDHI and WDT IP blocks.
> > > > >
> > > > > Signed-off-by: Lad Prabhakar
> > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > ---
> > > > > v2->v3
> > > > > - Moved DDIV_PACK() macro to patch #1
> > > > >
> > > > > v1->v2
> > > > > - Updated DDIV_PACK macro to accommodate width
> > > > > ---
> > > > >  drivers/clk/renesas/r9a09g057-cpg.c | 84 +++++++++++++++++++++++++++++
> > > > >  drivers/clk/renesas/rzv2h-cpg.h     |  4 ++
> > > > >  2 files changed, 88 insertions(+)
> > > > >
> > > > > diff --git a/drivers/clk/renesas/r9a09g057-cpg.c
> > > > > b/drivers/clk/renesas/r9a09g057-cpg.c
> > > > > index 9722b810e027..3ee32db5c0af 100644
> > > > > --- a/drivers/clk/renesas/r9a09g057-cpg.c
> > > > > +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> > > > > @@ -25,16 +25,31 @@ enum clk_ids {
> > > > >
> > > > >       /* PLL Clocks */
> > > > >       CLK_PLLCM33,
> > > > > +     CLK_PLLCLN,
> > > > >       CLK_PLLDTY,
> > > > >       CLK_PLLCA55,
> > > > >
> > > > >       /* Internal Core Clocks */
> > > > >       CLK_PLLCM33_DIV16,
> > > > > +     CLK_PLLCLN_DIV2,
> > > > > +     CLK_PLLCLN_DIV8,
> > > > > +     CLK_PLLCLN_DIV16,
> > > > > +     CLK_PLLDTY_ACPU,
> > > > > +     CLK_PLLDTY_ACPU_DIV4,
> > > > >
> > > > >       /* Module Clocks */
> > > > >       MOD_CLK_BASE,
> > > > >  };
> > > > >
> > > > > +static const struct clk_div_table dtable_2_64[] = {
> > > > > +     {0, 2},
> > > > > +     {1, 4},
> > > > > +     {2, 8},
> > > > > +     {3, 16},
> > > > > +     {4, 64},
> > > > > +     {0, 0},
> > > >
> > > > Is it ok to have {0, 2} first entry and {0, 0} last entry on the same table?
> > > >
> > > You mean is it prohibited to add (I haven't seen issues)?
> >
> > 2 different divider values{2, 0) for the value 0 in the table. You maybe correct.
> >
> AFAIK we add sentinel entry at the end of clk_div_table[], see below
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/clk/renesas/rcar-
> gen4-cpg.c?h=next-20240828#n415
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-
> next.git/tree/drivers/clk/renesas/r9a07g044-cpg.c?h=next-20240828#n80
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/clk/renesas/rcar-
> gen2-cpg.c?h=next-20240828#n202
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/clk/renesas/rcar-
> gen3-cpg.c?h=next-20240828#n327

If it is sentinel entry, then it is fine. I just commented because different divider values for same index.

Cheers,
Biju
Geert Uytterhoeven Aug. 29, 2024, 12:03 p.m. UTC | #6 
On Wed, Aug 28, 2024 at 11:38 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add clock and reset entries for GTM, RIIC, SDHI and WDT IP blocks.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3
> - Moved DDIV_PACK() macro to patch #1

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v6.12.

Gr{oetje,eeting}s,

                        Geert
diff mbox series

Patch

diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index 9722b810e027..3ee32db5c0af 100644
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -25,16 +25,31 @@  enum clk_ids {
 
 	/* PLL Clocks */
 	CLK_PLLCM33,
+	CLK_PLLCLN,
 	CLK_PLLDTY,
 	CLK_PLLCA55,
 
 	/* Internal Core Clocks */
 	CLK_PLLCM33_DIV16,
+	CLK_PLLCLN_DIV2,
+	CLK_PLLCLN_DIV8,
+	CLK_PLLCLN_DIV16,
+	CLK_PLLDTY_ACPU,
+	CLK_PLLDTY_ACPU_DIV4,
 
 	/* Module Clocks */
 	MOD_CLK_BASE,
 };
 
+static const struct clk_div_table dtable_2_64[] = {
+	{0, 2},
+	{1, 4},
+	{2, 8},
+	{3, 16},
+	{4, 64},
+	{0, 0},
+};
+
 static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
 	/* External Clock Inputs */
 	DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
@@ -43,23 +58,92 @@  static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
 
 	/* PLL Clocks */
 	DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
+	DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
 	DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
 	DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
 
 	/* Internal Core Clocks */
 	DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
 
+	DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
+	DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
+	DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
+
+	DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
+	DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
+
 	/* Core Clocks */
 	DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
 	DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
 };
 
 static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
+	DEF_MOD("gtm_0_pclk",			CLK_PLLCM33_DIV16, 4, 3, 2, 3),
+	DEF_MOD("gtm_1_pclk",			CLK_PLLCM33_DIV16, 4, 4, 2, 4),
+	DEF_MOD("gtm_2_pclk",			CLK_PLLCLN_DIV16, 4, 5, 2, 5),
+	DEF_MOD("gtm_3_pclk",			CLK_PLLCLN_DIV16, 4, 6, 2, 6),
+	DEF_MOD("gtm_4_pclk",			CLK_PLLCLN_DIV16, 4, 7, 2, 7),
+	DEF_MOD("gtm_5_pclk",			CLK_PLLCLN_DIV16, 4, 8, 2, 8),
+	DEF_MOD("gtm_6_pclk",			CLK_PLLCLN_DIV16, 4, 9, 2, 9),
+	DEF_MOD("gtm_7_pclk",			CLK_PLLCLN_DIV16, 4, 10, 2, 10),
+	DEF_MOD("wdt_0_clkp",			CLK_PLLCM33_DIV16, 4, 11, 2, 11),
+	DEF_MOD("wdt_0_clk_loco",		CLK_QEXTAL, 4, 12, 2, 12),
+	DEF_MOD("wdt_1_clkp",			CLK_PLLCLN_DIV16, 4, 13, 2, 13),
+	DEF_MOD("wdt_1_clk_loco",		CLK_QEXTAL, 4, 14, 2, 14),
+	DEF_MOD("wdt_2_clkp",			CLK_PLLCLN_DIV16, 4, 15, 2, 15),
+	DEF_MOD("wdt_2_clk_loco",		CLK_QEXTAL, 5, 0, 2, 16),
+	DEF_MOD("wdt_3_clkp",			CLK_PLLCLN_DIV16, 5, 1, 2, 17),
+	DEF_MOD("wdt_3_clk_loco",		CLK_QEXTAL, 5, 2, 2, 18),
 	DEF_MOD("scif_0_clk_pck",		CLK_PLLCM33_DIV16, 8, 15, 4, 15),
+	DEF_MOD("riic_8_ckm",			CLK_PLLCM33_DIV16, 9, 3, 4, 19),
+	DEF_MOD("riic_0_ckm",			CLK_PLLCLN_DIV16, 9, 4, 4, 20),
+	DEF_MOD("riic_1_ckm",			CLK_PLLCLN_DIV16, 9, 5, 4, 21),
+	DEF_MOD("riic_2_ckm",			CLK_PLLCLN_DIV16, 9, 6, 4, 22),
+	DEF_MOD("riic_3_ckm",			CLK_PLLCLN_DIV16, 9, 7, 4, 23),
+	DEF_MOD("riic_4_ckm",			CLK_PLLCLN_DIV16, 9, 8, 4, 24),
+	DEF_MOD("riic_5_ckm",			CLK_PLLCLN_DIV16, 9, 9, 4, 25),
+	DEF_MOD("riic_6_ckm",			CLK_PLLCLN_DIV16, 9, 10, 4, 26),
+	DEF_MOD("riic_7_ckm",			CLK_PLLCLN_DIV16, 9, 11, 4, 27),
+	DEF_MOD("sdhi_0_imclk",			CLK_PLLCLN_DIV8, 10, 3, 5, 3),
+	DEF_MOD("sdhi_0_imclk2",		CLK_PLLCLN_DIV8, 10, 4, 5, 4),
+	DEF_MOD("sdhi_0_clk_hs",		CLK_PLLCLN_DIV2, 10, 5, 5, 5),
+	DEF_MOD("sdhi_0_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6),
+	DEF_MOD("sdhi_1_imclk",			CLK_PLLCLN_DIV8, 10, 7, 5, 7),
+	DEF_MOD("sdhi_1_imclk2",		CLK_PLLCLN_DIV8, 10, 8, 5, 8),
+	DEF_MOD("sdhi_1_clk_hs",		CLK_PLLCLN_DIV2, 10, 9, 5, 9),
+	DEF_MOD("sdhi_1_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10),
+	DEF_MOD("sdhi_2_imclk",			CLK_PLLCLN_DIV8, 10, 11, 5, 11),
+	DEF_MOD("sdhi_2_imclk2",		CLK_PLLCLN_DIV8, 10, 12, 5, 12),
+	DEF_MOD("sdhi_2_clk_hs",		CLK_PLLCLN_DIV2, 10, 13, 5, 13),
+	DEF_MOD("sdhi_2_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14),
 };
 
 static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
+	DEF_RST(6, 13, 2, 30),		/* GTM_0_PRESETZ */
+	DEF_RST(6, 14, 2, 31),		/* GTM_1_PRESETZ */
+	DEF_RST(6, 15, 3, 0),		/* GTM_2_PRESETZ */
+	DEF_RST(7, 0, 3, 1),		/* GTM_3_PRESETZ */
+	DEF_RST(7, 1, 3, 2),		/* GTM_4_PRESETZ */
+	DEF_RST(7, 2, 3, 3),		/* GTM_5_PRESETZ */
+	DEF_RST(7, 3, 3, 4),		/* GTM_6_PRESETZ */
+	DEF_RST(7, 4, 3, 5),		/* GTM_7_PRESETZ */
+	DEF_RST(7, 5, 3, 6),		/* WDT_0_RESET */
+	DEF_RST(7, 6, 3, 7),		/* WDT_1_RESET */
+	DEF_RST(7, 7, 3, 8),		/* WDT_2_RESET */
+	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */
 	DEF_RST(9, 5, 4, 6),		/* SCIF_0_RST_SYSTEM_N */
+	DEF_RST(9, 8, 4, 9),		/* RIIC_0_MRST */
+	DEF_RST(9, 9, 4, 10),		/* RIIC_1_MRST */
+	DEF_RST(9, 10, 4, 11),		/* RIIC_2_MRST */
+	DEF_RST(9, 11, 4, 12),		/* RIIC_3_MRST */
+	DEF_RST(9, 12, 4, 13),		/* RIIC_4_MRST */
+	DEF_RST(9, 13, 4, 14),		/* RIIC_5_MRST */
+	DEF_RST(9, 14, 4, 15),		/* RIIC_6_MRST */
+	DEF_RST(9, 15, 4, 16),		/* RIIC_7_MRST */
+	DEF_RST(10, 0, 4, 17),		/* RIIC_8_MRST */
+	DEF_RST(10, 7, 4, 24),		/* SDHI_0_IXRST */
+	DEF_RST(10, 8, 4, 25),		/* SDHI_1_IXRST */
+	DEF_RST(10, 9, 4, 26),		/* SDHI_2_IXRST */
 };
 
 const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index 1c7a979ab790..1bd406c69015 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -31,6 +31,10 @@  struct ddiv {
 		.monbit = _monbit \
 	})
 
+#define CPG_CDDIV0		(0x400)
+
+#define CDDIV0_DIVCTL2	DDIV_PACK(CPG_CDDIV0, 8, 3, 2)
+
 /**
  * Definitions of CPG Core Clocks
  *