| Message ID | 20240913083724.1217691-2-quic_qianyu@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Add support for PCIe3 on x1e80100 | expand |
On Fri, Sep 13, 2024 at 01:37:20AM -0700, Qiang Yu wrote: > PCIe 3rd instance of X1E80100 support Gen 4x8 which needs different 8 lane > capable QMP PCIe PHY. Document Gen 4x8 PHY as separate module. > Nit: please use 'Gen 4 x8' - Mani > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > --- > .../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > index dcf4fa55fbba..680ec3113c2b 100644 > --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > @@ -41,6 +41,7 @@ properties: > - qcom,x1e80100-qmp-gen3x2-pcie-phy > - qcom,x1e80100-qmp-gen4x2-pcie-phy > - qcom,x1e80100-qmp-gen4x4-pcie-phy > + - qcom,x1e80100-qmp-gen4x8-pcie-phy > > reg: > minItems: 1 > @@ -172,6 +173,7 @@ allOf: > - qcom,sc8280xp-qmp-gen3x2-pcie-phy > - qcom,sc8280xp-qmp-gen3x4-pcie-phy > - qcom,x1e80100-qmp-gen4x4-pcie-phy > + - qcom,x1e80100-qmp-gen4x8-pcie-phy > then: > properties: > clocks: > @@ -201,6 +203,7 @@ allOf: > - qcom,sm8550-qmp-gen4x2-pcie-phy > - qcom,sm8650-qmp-gen4x2-pcie-phy > - qcom,x1e80100-qmp-gen4x2-pcie-phy > + - qcom,x1e80100-qmp-gen4x8-pcie-phy > then: > properties: > resets: > -- > 2.34.1 >
On Fri, Sep 13, 2024 at 01:37:20AM -0700, Qiang Yu wrote: > PCIe 3rd instance of X1E80100 support Gen 4x8 which needs different 8 lane > capable QMP PCIe PHY. Document Gen 4x8 PHY as separate module. And this is really different hardware? Not just different number of lanes? We discussed it, but I don't see the explanation in commit msg. > > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > --- > .../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > index dcf4fa55fbba..680ec3113c2b 100644 > --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > @@ -41,6 +41,7 @@ properties: > - qcom,x1e80100-qmp-gen3x2-pcie-phy > - qcom,x1e80100-qmp-gen4x2-pcie-phy > - qcom,x1e80100-qmp-gen4x4-pcie-phy > + - qcom,x1e80100-qmp-gen4x8-pcie-phy > > reg: > minItems: 1 > @@ -172,6 +173,7 @@ allOf: > - qcom,sc8280xp-qmp-gen3x2-pcie-phy > - qcom,sc8280xp-qmp-gen3x4-pcie-phy > - qcom,x1e80100-qmp-gen4x4-pcie-phy > + - qcom,x1e80100-qmp-gen4x8-pcie-phy > then: > properties: > clocks: > @@ -201,6 +203,7 @@ allOf: > - qcom,sm8550-qmp-gen4x2-pcie-phy > - qcom,sm8650-qmp-gen4x2-pcie-phy > - qcom,x1e80100-qmp-gen4x2-pcie-phy Hm, why 4x4 is not here? Best regards, Krzysztof
On 9/13/2024 9:37 PM, Manivannan Sadhasivam wrote: > On Fri, Sep 13, 2024 at 01:37:20AM -0700, Qiang Yu wrote: >> PCIe 3rd instance of X1E80100 support Gen 4x8 which needs different 8 lane >> capable QMP PCIe PHY. Document Gen 4x8 PHY as separate module. >> > Nit: please use 'Gen 4 x8' Will update in next version patch. Thanks, Qiang > > - Mani > >> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> >> --- >> .../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml >> index dcf4fa55fbba..680ec3113c2b 100644 >> --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml >> +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml >> @@ -41,6 +41,7 @@ properties: >> - qcom,x1e80100-qmp-gen3x2-pcie-phy >> - qcom,x1e80100-qmp-gen4x2-pcie-phy >> - qcom,x1e80100-qmp-gen4x4-pcie-phy >> + - qcom,x1e80100-qmp-gen4x8-pcie-phy >> >> reg: >> minItems: 1 >> @@ -172,6 +173,7 @@ allOf: >> - qcom,sc8280xp-qmp-gen3x2-pcie-phy >> - qcom,sc8280xp-qmp-gen3x4-pcie-phy >> - qcom,x1e80100-qmp-gen4x4-pcie-phy >> + - qcom,x1e80100-qmp-gen4x8-pcie-phy >> then: >> properties: >> clocks: >> @@ -201,6 +203,7 @@ allOf: >> - qcom,sm8550-qmp-gen4x2-pcie-phy >> - qcom,sm8650-qmp-gen4x2-pcie-phy >> - qcom,x1e80100-qmp-gen4x2-pcie-phy >> + - qcom,x1e80100-qmp-gen4x8-pcie-phy >> then: >> properties: >> resets: >> -- >> 2.34.1 >>
On 9/16/2024 11:15 PM, Krzysztof Kozlowski wrote: > On Fri, Sep 13, 2024 at 01:37:20AM -0700, Qiang Yu wrote: >> PCIe 3rd instance of X1E80100 support Gen 4x8 which needs different 8 lane >> capable QMP PCIe PHY. Document Gen 4x8 PHY as separate module. > And this is really different hardware? Not just different number of lanes? We discussed it, but I don't see the explanation in commit msg. Yes, PCIe3 use a different phy that supports 8 lanes and provides additional register set, txz and rxz. It is not a bifurcation mode which actually combines two same phys like PCIe6a. It's also not just different number of lanes. Will explain this in commit msg. Thanks, Qiang >> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> >> --- >> .../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml >> index dcf4fa55fbba..680ec3113c2b 100644 >> --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml >> +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml >> @@ -41,6 +41,7 @@ properties: >> - qcom,x1e80100-qmp-gen3x2-pcie-phy >> - qcom,x1e80100-qmp-gen4x2-pcie-phy >> - qcom,x1e80100-qmp-gen4x4-pcie-phy >> + - qcom,x1e80100-qmp-gen4x8-pcie-phy >> >> reg: >> minItems: 1 >> @@ -172,6 +173,7 @@ allOf: >> - qcom,sc8280xp-qmp-gen3x2-pcie-phy >> - qcom,sc8280xp-qmp-gen3x4-pcie-phy >> - qcom,x1e80100-qmp-gen4x4-pcie-phy >> + - qcom,x1e80100-qmp-gen4x8-pcie-phy >> then: >> properties: >> clocks: >> @@ -201,6 +203,7 @@ allOf: >> - qcom,sm8550-qmp-gen4x2-pcie-phy >> - qcom,sm8650-qmp-gen4x2-pcie-phy >> - qcom,x1e80100-qmp-gen4x2-pcie-phy > Hm, why 4x4 is not here? > > Best regards, > Krzysztof
On 19.09.2024 4:03 PM, Qiang Yu wrote: > > On 9/16/2024 11:15 PM, Krzysztof Kozlowski wrote: >> On Fri, Sep 13, 2024 at 01:37:20AM -0700, Qiang Yu wrote: >>> PCIe 3rd instance of X1E80100 support Gen 4x8 which needs different 8 lane >>> capable QMP PCIe PHY. Document Gen 4x8 PHY as separate module. >> And this is really different hardware? Not just different number of lanes? We discussed it, but I don't see the explanation in commit msg. > Yes, PCIe3 use a different phy that supports 8 lanes and provides > additional register set, txz and rxz. It is not a bifurcation mode which > actually combines two same phys like PCIe6a. It's also not just different > number of lanes. Will explain this in commit msg. Krzysztof, this PHY is new and has a different hardware revision (v6.30 as opposed to v6.20? of the other ones) Konrad
On 19/09/2024 17:37, Konrad Dybcio wrote: > On 19.09.2024 4:03 PM, Qiang Yu wrote: >> >> On 9/16/2024 11:15 PM, Krzysztof Kozlowski wrote: >>> On Fri, Sep 13, 2024 at 01:37:20AM -0700, Qiang Yu wrote: >>>> PCIe 3rd instance of X1E80100 support Gen 4x8 which needs different 8 lane >>>> capable QMP PCIe PHY. Document Gen 4x8 PHY as separate module. >>> And this is really different hardware? Not just different number of lanes? We discussed it, but I don't see the explanation in commit msg. >> Yes, PCIe3 use a different phy that supports 8 lanes and provides >> additional register set, txz and rxz. It is not a bifurcation mode which >> actually combines two same phys like PCIe6a. It's also not just different >> number of lanes. Will explain this in commit msg. > > Krzysztof, this PHY is new and has a different hardware revision (v6.30 as > opposed to v6.20? of the other ones) It's fine for me then, but I expect commit msg to say this. For I am a bear of very little brain, and I forget the topic right after I close the email. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index dcf4fa55fbba..680ec3113c2b 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -41,6 +41,7 @@ properties: - qcom,x1e80100-qmp-gen3x2-pcie-phy - qcom,x1e80100-qmp-gen4x2-pcie-phy - qcom,x1e80100-qmp-gen4x4-pcie-phy + - qcom,x1e80100-qmp-gen4x8-pcie-phy reg: minItems: 1 @@ -172,6 +173,7 @@ allOf: - qcom,sc8280xp-qmp-gen3x2-pcie-phy - qcom,sc8280xp-qmp-gen3x4-pcie-phy - qcom,x1e80100-qmp-gen4x4-pcie-phy + - qcom,x1e80100-qmp-gen4x8-pcie-phy then: properties: clocks: @@ -201,6 +203,7 @@ allOf: - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen4x2-pcie-phy - qcom,x1e80100-qmp-gen4x2-pcie-phy + - qcom,x1e80100-qmp-gen4x8-pcie-phy then: properties: resets:
PCIe 3rd instance of X1E80100 support Gen 4x8 which needs different 8 lane capable QMP PCIe PHY. Document Gen 4x8 PHY as separate module. Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 3 +++ 1 file changed, 3 insertions(+)