From patchwork Thu Oct 31 07:02:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cody Eksal X-Patchwork-Id: 13857627 Received: from thales.epochal.quest (thales.epochal.quest [51.222.15.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3177F14AD02; Thu, 31 Oct 2024 07:03:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=51.222.15.28 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730358215; cv=none; b=Ys5K08I0+m+Mo5ZGM+iE394SHhHNqiU4mNG7yaF0PsNNUUrq9dowDMqSWB2x/6bjAjCQikYAwFR8Qdo/k2t3JUr2Yz83MWBnoyQPBv6kfTt6A++pvYhypT6GCYKtYy4AjJPx4NdwGxEQ7TyC5vAIHyNsvwOwAff20sM4ej98ujw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730358215; c=relaxed/simple; bh=gPKWhriD3pnIH1Uk3cfPOThE675psdPThf952AsBt2A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=K+hFD0wUcqVwZQSYPqHh0HRDLeH4iwOun91sMoZYkIvtMgXPk8i15MqbdG1HNLbbBZVlafPq9qKb3bObEuLYOie0RZDJqDPJkkXdYpw3CimtvuxTGEjjW/sBmUJkTUOGj80pVa/EGURlv1axrZXSjvu8RvlmHdPx9OOvY9QNAh0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=epochal.quest; spf=pass smtp.mailfrom=epochal.quest; dkim=pass (2048-bit key) header.d=epochal.quest header.i=@epochal.quest header.b=LEtUiATi; arc=none smtp.client-ip=51.222.15.28 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=epochal.quest Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=epochal.quest Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=epochal.quest header.i=@epochal.quest header.b="LEtUiATi" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=epochal.quest; s=default; t=1730358205; bh=gPKWhriD3pnIH1Uk3cfPOThE675psdPThf952AsBt2A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LEtUiATid8r890K9Gp/niU0S+v6+BsFNh4OPspSgwA+SLTtetM/CQDrRxQCvuAn/E afPq/dWezuNge28FyOaepgHgGMmw4mZ/tjSwVhDokwiZvdZIl1ordBTKaAPyKnzlrg pXm1ftRf6ecQsMWbsQsdeCKLGFjZrSG6wEKvg7DXBrccX/Rh4cVaDDjXut0Zq8VwaL /ErJoJAqjkWRN2h37PsRIBGc128Ogk7lM5sgxc+nhZNVDMm9P1qPyJqpfTdyDJz7dB VAaNtG+MZN8N+ZU2UR/OF/FONIqPf2GU8d988wM0D1OAxzsd3/0TnLaynIzsAGtb9f 8HhYnOcq1IsWQ== X-Virus-Scanned: by epochal.quest From: Cody Eksal To: Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Conor Dooley , Greg Kroah-Hartman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Maxime Ripard , Nishanth Menon , "Rafael J. Wysocki" , Rob Herring , Vinod Koul , Viresh Kumar , Viresh Kumar , Yangtao Li , Parthiban , Andre Przywara , Cody Eksal , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 08/13] clk: sunxi-ng: a100: enable MMC clock reparenting Date: Thu, 31 Oct 2024 04:02:21 -0300 Message-ID: <20241031070232.1793078-9-masterr3c0rd@epochal.quest> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241031070232.1793078-1-masterr3c0rd@epochal.quest> References: <20241031070232.1793078-1-masterr3c0rd@epochal.quest> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 During testing, it was noted that MMC would fail to initialize, with "mmc: fatal err update clk timeout" being printed in the log. It was found that CLK_SET_RATE_NO_REPARENT was set on the MMC controllers, and that removing this allows MMC to initialize. Therefore, remove CLK_SET_RATE_NO_REPARENT from mmc0/1/2. Signed-off-by: Cody Eksal Reviewed-by: Andre Przywara --- drivers/clk/sunxi-ng/ccu-sun50i-a100.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a100.c b/drivers/clk/sunxi-ng/ccu-sun50i-a100.c index bbaa82978716..a59e420b195d 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a100.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a100.c @@ -436,7 +436,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830, 24, 2, /* mux */ BIT(31), /* gate */ 2, /* post-div */ - CLK_SET_RATE_NO_REPARENT); + 0); static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834, 0, 4, /* M */ @@ -444,7 +444,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834, 24, 2, /* mux */ BIT(31), /* gate */ 2, /* post-div */ - CLK_SET_RATE_NO_REPARENT); + 0); static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838, 0, 4, /* M */ @@ -452,7 +452,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838, 24, 2, /* mux */ BIT(31), /* gate */ 2, /* post-div */ - CLK_SET_RATE_NO_REPARENT); + 0); static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0); static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);