| Message ID | 20241106-mbly-clk-v2-7-84cfefb3f485@bootlin.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Headers | show |
| Series | Usable clocks on Mobileye EyeQ5 & EyeQ6H | expand |
Quoting Théo Lebrun (2024-11-06 08:03:58) > Previous setup was: > - pll-cpu clock registered from driver at of_clk_init(); > - occ-cpu clock registered from DT using fixed-factor-clock compatible. > > Now that drivers/clk/clk-eyeq.c supports registering fixed factors, use > that capability to register occ-cpu. > > Also switch from hard-coded index 0 for pll-cpu to using the > EQ6HC_CENTRAL_PLL_CPU constant by exposed dt-bindings headers. > > occ-cpu is exposed at of_clk_init() because it gets used by both the DT > CPU nodes and the GIC timer. > > Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> > --- Applied to clk-next
diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index 542909085bcedb0f6b5b3cffbdb5761da9981cbc..a042e9735b68f85c1ad79ec963b0268410b87ad4 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -695,12 +695,19 @@ builtin_platform_driver(eqc_driver); /* Required early for GIC timer. */ static const struct eqc_pll eqc_eyeq6h_central_early_plls[] = { - { .index = 0, .name = "pll-cpu", .reg64 = 0x02C }, + { .index = EQ6HC_CENTRAL_PLL_CPU, .name = "pll-cpu", .reg64 = 0x02C }, +}; + +static const struct eqc_fixed_factor eqc_eyeq6h_central_early_fixed_factors[] = { + { EQ6HC_CENTRAL_CPU_OCC, "occ-cpu", 1, 1, EQ6HC_CENTRAL_PLL_CPU }, }; static const struct eqc_early_match_data eqc_eyeq6h_central_early_match_data __initconst = { .early_pll_count = ARRAY_SIZE(eqc_eyeq6h_central_early_plls), .early_plls = eqc_eyeq6h_central_early_plls, + + .early_fixed_factor_count = ARRAY_SIZE(eqc_eyeq6h_central_early_fixed_factors), + .early_fixed_factors = eqc_eyeq6h_central_early_fixed_factors, }; /* Required early for UART. */
Previous setup was: - pll-cpu clock registered from driver at of_clk_init(); - occ-cpu clock registered from DT using fixed-factor-clock compatible. Now that drivers/clk/clk-eyeq.c supports registering fixed factors, use that capability to register occ-cpu. Also switch from hard-coded index 0 for pll-cpu to using the EQ6HC_CENTRAL_PLL_CPU constant by exposed dt-bindings headers. occ-cpu is exposed at of_clk_init() because it gets used by both the DT CPU nodes and the GIC timer. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> --- drivers/clk/clk-eyeq.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)