From patchwork Sat Nov 16 08:18:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13877520 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16C4638382; Sat, 16 Nov 2024 08:19:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731745168; cv=none; b=SX0jhgVy1HcZZvr9/yTlI4HpC01hufVz4S4YX7P2e3sUAn4XD6fRxDTNCmiNJ8cWqAvelbGBulZFQHoC5D9ucr/ci6Pe/J4k5FqsF2IEyrmZkl2N5fVMzDqpcco5eOtinxIkks72K7MJMPrPgrLky7CO0Qxgc/D1xLGz+gORr8Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731745168; c=relaxed/simple; bh=CUcpugj82iytRhkjUR6sYhraDFJqW4jyvGhHZ4iOlOk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nMY3sAtuQlZrOfDMqWik3dcBhlNcmuS9eS+MRRtHmWQS/BHU9mh0sZCF7dEf5ZiGvaqzQvs6ahgpeUPVZ3z2Pf5pBrHVHARUq7VUSdktt5QE4FIxHSwprdzKBqgccUteJYcQJ5RvkTOMXHyBwnhvKobKejp8b+MIrpv4VE3eWJc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=P7DdJ2rG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="P7DdJ2rG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0D218C4CEC3; Sat, 16 Nov 2024 08:19:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731745167; bh=CUcpugj82iytRhkjUR6sYhraDFJqW4jyvGhHZ4iOlOk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=P7DdJ2rGanYqWy+VDkD9X3pI8THRiN03JohFbl667luBJl7Yn3yoG/P63tawO39Jq 8rQafq1KqXYnU0O+jt5uek9eCUHJCy9Iuu1c9wykYNnOQml7FtbLFRNqNg8ToIiyo5 a+pIQxDoS5N2TAYSqYah0QyOv6PpikXr0+zAk0wD479Z04Q/yXmZejx8tfc0mTY2sb M94xBZXdDPhT49KaBvCZP2/tVfWldWhDWe4YOVB490prK45are4cqYB/1rkK39C+NO QeZ8asnNf4g/LDsdrzT2I14S/DNCRL+CPydhtUjknBoIVfEs42VOCmzCT/G6Iesicy V6+J902OoXlvg== From: Lorenzo Bianconi Date: Sat, 16 Nov 2024 09:18:24 +0100 Subject: [PATCH v3 3/6] PCI: mediatek-gen3: Move reset/assert callbacks in .power_up() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241116-pcie-en7581-fixes-v3-3-f7add3afc27e@kernel.org> References: <20241116-pcie-en7581-fixes-v3-0-f7add3afc27e@kernel.org> In-Reply-To: <20241116-pcie-en7581-fixes-v3-0-f7add3afc27e@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 In order to make the code more readable, the reset_control_bulk_assert() for PHY reset lines is moved to make it pair with reset_control_bulk_deassert() in mtk_pcie_power_up() and mtk_pcie_en7581_power_up(). The same change is done for reset_control_assert() used to assert MAC reset line. Introduce PCIE_MTK_RESET_TIME_US macro for the time needed to complete PCIe reset on MediaTek controller. Signed-off-by: Lorenzo Bianconi Reviewed-by: AngeloGioacchino Del Regno --- drivers/pci/controller/pcie-mediatek-gen3.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 3cfcb45d31508142d28d338ff213f70de9b4e608..2b80edd4462ad4e9f2a5d192db7f99307113eb8a 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -125,6 +125,8 @@ #define MAX_NUM_PHY_RESETS 3 +#define PCIE_MTK_RESET_TIME_US 10 + /* Time in ms needed to complete PCIe reset on EN7581 SoC */ #define PCIE_EN7581_RESET_TIME_MS 100 @@ -912,6 +914,14 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) int err; u32 val; + /* + * The controller may have been left out of reset by the bootloader + * so make sure that we get a clean start by asserting resets here. + */ + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, + pcie->phy_resets); + reset_control_assert(pcie->mac_reset); + /* * Wait for the time needed to complete the bulk assert in * mtk_pcie_setup for EN7581 SoC. @@ -986,6 +996,15 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie) struct device *dev = pcie->dev; int err; + /* + * The controller may have been left out of reset by the bootloader + * so make sure that we get a clean start by asserting resets here. + */ + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, + pcie->phy_resets); + reset_control_assert(pcie->mac_reset); + usleep_range(PCIE_MTK_RESET_TIME_US, 2 * PCIE_MTK_RESET_TIME_US); + /* PHY power on and enable pipe clock */ err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); if (err) { @@ -1070,14 +1089,6 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie) * counter since the bulk is shared. */ reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); - /* - * The controller may have been left out of reset by the bootloader - * so make sure that we get a clean start by asserting resets here. - */ - reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); - - reset_control_assert(pcie->mac_reset); - usleep_range(10, 20); /* Don't touch the hardware registers before power up */ err = pcie->soc->power_up(pcie);