From patchwork Wed Nov 20 07:01:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao via B4 Relay X-Patchwork-Id: 13880766 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45991158868; Wed, 20 Nov 2024 07:01:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732086076; cv=none; b=FLTWsTwz4szCoNZfwcB0fTynFsp/0LE7Za8iFwCPeWGmrR7aZ5tDsplvOMD9jTUSUozEV1z5ZP7XCXhtmg7ozCZUQRiUqd6vj/0X+pWZCJ18m97N1ZPYV575ntY2TPh2ANKy7+sLcS7jU2+jkoMEVljxwXWCVNUU0DFjj1nopr8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732086076; c=relaxed/simple; bh=7OixjdD2m8/UmdxhBFIAm4/7uSUL3SJDwCAZXPIjzio=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IPexQTyV/Z+CPrwFpTHfp9gtCMiuLO3ehNTDqiI9OOvJayrgkC64XKGS+IhnZ2U0R9tuhTQ48Gd29SnHl0VR1YbAuK29UKes95w+i5gj3yZWmLcYwqczd8IPmYIOoqCgb9UhB4eUrUpZ40N/wQNmIbzVEutQ6bwqGnN8N9jHvCI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SHWu7HRx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SHWu7HRx" Received: by smtp.kernel.org (Postfix) with ESMTPS id C9CBEC4CED9; Wed, 20 Nov 2024 07:01:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732086075; bh=7OixjdD2m8/UmdxhBFIAm4/7uSUL3SJDwCAZXPIjzio=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=SHWu7HRxU2R+pyPZ6PnTe6bcZrBLPsHvvffWO1rxvC8FrtExFFXi47hXbf1YcwCY4 KPF/xRUcIyXQmZutpGtYsl6RQLNq/IzYALYGA3rdznI97IQxrHcT6iK+mcioyxmYqU 52NkVxyQ+BW9/EbaKtZ97RKCK6BVJVUiDAWfKoIK9i+Ari/naizW1Q8OnJQHOyRUXV Lqeu/IZ/yMAPwLL1rYbkf1P/S7IfBmgvZJmf9W766EnuBAgLZxDUfvUj1sEbXsCxJf HfII8K2qdLnRl8gkTsJeH7nIyjRzj2XqDRX1wvgPLbuAJUkTTxF2/jC0nsrYbA5Qcm MMVqEPR7XB5Ug== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B95F9D6E2CA; Wed, 20 Nov 2024 07:01:15 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Wed, 20 Nov 2024 15:01:14 +0800 Subject: [PATCH v2 2/5] dt-bindings: clock: add Amlogic A5 SCMI clock controller support Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241120-a5-clk-v2-2-1208621e961d@amlogic.com> References: <20241120-a5-clk-v2-0-1208621e961d@amlogic.com> In-Reply-To: <20241120-a5-clk-v2-0-1208621e961d@amlogic.com> To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chuan Liu , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1732086073; l=1985; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=lkr1GZx7K1kssXy2RilRTA0K2DTWj4ijmI36kNCn2FY=; b=WwJlJxcYgAA0jMGr5xGeO8lMYfZSfFQrigWHeb+nMJ7HK2hQ4DaCV1JCZeu3pt6v6H0n0pNdM xWxGFLvrznVBfaSg/vaK0IKX9qH5liFLa7AC5IkOUP3821nw9jxew/H X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Chuan Liu Add the SCMI clock controller dt-bindings for Amlogic A5 SoC family. Signed-off-by: Chuan Liu Reviewed-by: Rob Herring (Arm) Signed-off-by: Xianwei Zhao --- include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 ++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h b/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h new file mode 100644 index 000000000000..1bf027d0110a --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu + */ + +#ifndef __AMLOGIC_A5_SCMI_CLKC_H +#define __AMLOGIC_A5_SCMI_CLKC_H + +#define CLKID_OSC 0 +#define CLKID_SYS_CLK 1 +#define CLKID_AXI_CLK 2 +#define CLKID_CPU_CLK 3 +#define CLKID_DSU_CLK 4 +#define CLKID_GP1_PLL 5 +#define CLKID_FIXED_PLL_DCO 6 +#define CLKID_FIXED_PLL 7 +#define CLKID_ACLKM 8 +#define CLKID_SYS_PLL_DIV16 9 +#define CLKID_CPU_CLK_DIV16 10 +#define CLKID_FCLK_50M_PREDIV 11 +#define CLKID_FCLK_50M_DIV 12 +#define CLKID_FCLK_50M 13 +#define CLKID_FCLK_DIV2_DIV 14 +#define CLKID_FCLK_DIV2 15 +#define CLKID_FCLK_DIV2P5_DIV 16 +#define CLKID_FCLK_DIV2P5 17 +#define CLKID_FCLK_DIV3_DIV 18 +#define CLKID_FCLK_DIV3 19 +#define CLKID_FCLK_DIV4_DIV 20 +#define CLKID_FCLK_DIV4 21 +#define CLKID_FCLK_DIV5_DIV 22 +#define CLKID_FCLK_DIV5 23 +#define CLKID_FCLK_DIV7_DIV 24 +#define CLKID_FCLK_DIV7 25 +#define CLKID_SYS_MMC_PCLK 26 +#define CLKID_SYS_CPU_CTRL 27 +#define CLKID_SYS_IRQ_CTRL 28 +#define CLKID_SYS_GIC 29 +#define CLKID_SYS_BIG_NIC 30 +#define CLKID_AXI_SYS_NIC 31 +#define CLKID_AXI_CPU_DMC 32 + +#endif /* __AMLOGIC_A5_SCMI_CLKC_H */