| Message ID | 20241220103825.3509421-2-kever.yang@rock-chips.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | rockchip: Add rk3562 support | expand |
On Fri, Dec 20, 2024 at 06:37:47PM +0800, Kever Yang wrote: > Document the device tree bindings of the rockchip rk3562 SoC > clock and reset unit. > > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > --- > > .../bindings/clock/rockchip,rk3562-cru.yaml | 62 +++++++++++++++++++ > 1 file changed, 62 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml > > diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml > new file mode 100644 > index 000000000000..aa8dedf2bfce > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml > @@ -0,0 +1,62 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/rockchip,rk3562-cru.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip rk3562 Clock and Reset Control Module > + > +maintainers: > + - Elaine Zhang <zhangqing@rock-chips.com> > + - Heiko Stuebner <heiko@sntech.de> > + > +description: > + The RK3562 clock controller generates the clock and also implements a reset > + controller for SoC peripherals. For example it provides SCLK_UART2 and > + PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART > + module. > + > +properties: > + compatible: > + const: rockchip,rk3562-cru > + > + reg: > + maxItems: 1 > + > + "#clock-cells": > + const: 1 > + > + "#reset-cells": > + const: 1 > + > + clocks: > + maxItems: 2 > + > + clock-names: > + items: > + - const: xin24m > + - const: xin32k > + > + rockchip,grf: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Phandle to the syscon managing the "general register files" (GRF), > + if missing pll rates are not changeable, due to the missing pll > + lock status. Two questions: - Why would it ever be missing? Seems like you should make it required. - Why is it not possible to look the grf up by compatible rather than phandle? Cheers, Conor. > + > +required: > + - compatible > + - reg > + - "#clock-cells" > + - "#reset-cells" > + > +additionalProperties: false > + > +examples: > + - | > + clock-controller@ff100000 { > + compatible = "rockchip,rk3562-cru"; > + reg = <0xff100000 0x40000>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > -- > 2.25.1 > >
Hi Conor, On 2024/12/22 22:51, Conor Dooley wrote: > On Fri, Dec 20, 2024 at 06:37:47PM +0800, Kever Yang wrote: >> Document the device tree bindings of the rockchip rk3562 SoC >> clock and reset unit. >> >> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> >> --- >> >> .../bindings/clock/rockchip,rk3562-cru.yaml | 62 +++++++++++++++++++ >> 1 file changed, 62 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml >> >> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml >> new file mode 100644 >> index 000000000000..aa8dedf2bfce >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml >> @@ -0,0 +1,62 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/rockchip,rk3562-cru.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Rockchip rk3562 Clock and Reset Control Module >> + >> +maintainers: >> + - Elaine Zhang <zhangqing@rock-chips.com> >> + - Heiko Stuebner <heiko@sntech.de> >> + >> +description: >> + The RK3562 clock controller generates the clock and also implements a reset >> + controller for SoC peripherals. For example it provides SCLK_UART2 and >> + PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART >> + module. >> + >> +properties: >> + compatible: >> + const: rockchip,rk3562-cru >> + >> + reg: >> + maxItems: 1 >> + >> + "#clock-cells": >> + const: 1 >> + >> + "#reset-cells": >> + const: 1 >> + >> + clocks: >> + maxItems: 2 >> + >> + clock-names: >> + items: >> + - const: xin24m >> + - const: xin32k >> + >> + rockchip,grf: >> + $ref: /schemas/types.yaml#/definitions/phandle >> + description: >> + Phandle to the syscon managing the "general register files" (GRF), >> + if missing pll rates are not changeable, due to the missing pll >> + lock status. > Two questions: > - Why would it ever be missing? Seems like you should make it required. This may not need for some of SoC, for the rk3562, we don't need it, I will remove it. Thanks, - Kever > - Why is it not possible to look the grf up by compatible rather than > phandle? > > Cheers, > Conor. > >> + >> +required: >> + - compatible >> + - reg >> + - "#clock-cells" >> + - "#reset-cells" >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + clock-controller@ff100000 { >> + compatible = "rockchip,rk3562-cru"; >> + reg = <0xff100000 0x40000>; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + }; >> -- >> 2.25.1 >> >>
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml new file mode 100644 index 000000000000..aa8dedf2bfce --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3562-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip rk3562 Clock and Reset Control Module + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: + The RK3562 clock controller generates the clock and also implements a reset + controller for SoC peripherals. For example it provides SCLK_UART2 and + PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART + module. + +properties: + compatible: + const: rockchip,rk3562-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: xin24m + - const: xin32k + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@ff100000 { + compatible = "rockchip,rk3562-cru"; + reg = <0xff100000 0x40000>; + #clock-cells = <1>; + #reset-cells = <1>; + };
Document the device tree bindings of the rockchip rk3562 SoC clock and reset unit. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> --- .../bindings/clock/rockchip,rk3562-cru.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml