From patchwork Tue Feb 18 18:26:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ahmad Fatoum X-Patchwork-Id: 13980472 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 786311EB5DC for ; Tue, 18 Feb 2025 18:27:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739903248; cv=none; b=rjNHgOogtzGhroqN7OYxsYP98fuydAehbtT6EhGJrmsPUfMMoiEmRQttcFbzcWZQxO0wz06sR+7/FSrdSLUNxEcTSSxpp9T6nAiEFMLfKrOJK4mBgw3PU6/aSn9T0wIPvj8fhjoBT50/n/3TfSRBHSIBjWZwUQ88ES/TCbY/Reo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739903248; c=relaxed/simple; bh=zNE/DNv8Rppeo9YS/X0VZcm7JvRezuQoHrQ8Y+6T7r0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CBUetHAvegy9ME0M31VzQDbTPlvygWa4JHPYbBNJ96v0A1KEjfQMx8jhyUuSebIxOGsxOb3YkcAYcMG6wRZhJw6bWapU2UbM5ozHv+kvFk4JeJSH8GdxX5z6K5nbPcrQm+ybagLs7/9yVVH7SAuqNsBMjodAVM7uAsf/O/kP0kw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1tkSIy-0006Bf-13; Tue, 18 Feb 2025 19:26:48 +0100 Received: from dude05.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::54]) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1tkSIx-001dVA-1V; Tue, 18 Feb 2025 19:26:47 +0100 Received: from localhost ([::1] helo=dude05.red.stw.pengutronix.de) by dude05.red.stw.pengutronix.de with esmtp (Exim 4.96) (envelope-from ) id 1tkSIx-00A9Hm-1B; Tue, 18 Feb 2025 19:26:47 +0100 From: Ahmad Fatoum Date: Tue, 18 Feb 2025 19:26:41 +0100 Subject: [PATCH v4 1/6] dt-bindings: clock: imx8m: document nominal/overdrive properties Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250218-imx8m-clk-v4-1-b7697dc2dcd0@pengutronix.de> References: <20250218-imx8m-clk-v4-0-b7697dc2dcd0@pengutronix.de> In-Reply-To: <20250218-imx8m-clk-v4-0-b7697dc2dcd0@pengutronix.de> To: Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Frank Li , Pengutronix Kernel Team , Fabio Estevam , Abel Vesa , Marek Vasut Cc: linux-clk@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Ahmad Fatoum X-Mailer: b4 0.14.2 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: a.fatoum@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-clk@vger.kernel.org The imx8m-clock.yaml binding covers the clock controller inside all of the i.MX8M Q/M/N/P SoCs. All of them have in common that they support two operating modes: nominal and overdrive mode. While the overdrive mode allows for higher frequencies for many IPs, the nominal mode needs a lower SoC voltage, thereby reducing heat generation and power usage. As increasing clock rates beyond the maximum permitted by the supplied SoC voltage can lead to difficult to debug issues, device tree consumers would benefit from knowing what mode is active to enforce the clock rate limits that come with it. To facilitate this, extend the clock controller bindings with an optional fsl,operating-mode property. This intentionally allows the absence of the property, because there is no default suitable for all boards: For i.MX8M Mini and Nano, the kernel SoC DTSIs has assigned-clock-rates that are all achievable in nominal mode. For i.MX8MP, there are some rates only validated for overdrive mode. But even for the i.MX8M Mini/Nano boards, we don't know what rates they may configure at runtime, so it has not been possible so far to infer from just the device tree what the mode is. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Ahmad Fatoum --- Documentation/devicetree/bindings/clock/imx8m-clock.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml index c643d4a814786a1fc7e559140fe58911990f71bb..4fec558327027faa0a8d2a15699c03713da2deae 100644 --- a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml @@ -43,6 +43,13 @@ properties: ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m-clock.h for the full list of i.MX8M clock IDs. + fsl,operating-mode: + $ref: /schemas/types.yaml#/definitions/string + enum: [nominal, overdrive] + description: + The operating mode of the SoC. This affects the maximum clock rates that + can safely be configured by the clock controller. + required: - compatible - reg @@ -109,6 +116,7 @@ examples: <&clk_ext3>, <&clk_ext4>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; + fsl,operating-mode = "nominal"; }; - |