From patchwork Fri Feb 21 07:50:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Friday Yang X-Patchwork-Id: 13984941 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5711C1FFC68; Fri, 21 Feb 2025 07:51:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740124274; cv=none; b=aDYoiQ/nS/LjEmcqxtArN3uqAASnmCmQIV/W4rHpPGDrpf8/kU+POS6qM23m+gnmjMBwb8+sE4b/rGoU8ucjMuUGy1dCgVr/ZBAmnhRgryc3RK1G/4cI56apyKPqH3XrktxudmamcYJdwEUSluYbCHqQOTr8s4ECVSpzrdH0eWA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740124274; c=relaxed/simple; bh=HoOYcU9Efh6fRP1Jy8FEHuTrJiKVGL70I52g6xlThLI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RnlKyH6PPpzQPCFavTrMgfHVr/AlVdbZjWXaGfQjU8Q3FySxiDCLhABZrANvp//fXVMHtTvz+OCwJOgzN/VbLXdiWu1saloHDdv9z9SCbjWggPVmH4vLedZ6gGTaHprREZO2xjuW2H2V2FhDTdIG2mv1XGCQUjfKDs7m/a4rqdQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=e4LgzAyW; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="e4LgzAyW" X-UUID: 9a087560f02811efaae1fd9735fae912-20250221 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Tf9yY5GNo3wwGs60RVZAwM1Begrqy8p8fwcUqxff3dw=; b=e4LgzAyWpa/jusC1ZuUHXgWWHIDLYC7Pt4uxVy+ZSgUuqTgaIYKipStvuAxzp7gohVydJU2E/GScMNZAybybertqp01//RoeC/m+AYfR7QAO3420FjVVT2IQiiuEv8lrbbUbDrgoE+iJZ9hsbrT6VHxbsvgfGS+q3DTj9tcAHH4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.46,REQID:3c2225cc-7e39-4f68-9fe9-b4d76cc5aec1,IP:0,U RL:0,TC:0,Content:0,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-30 X-CID-META: VersionHash:60aa074,CLOUDID:da4068b5-a2a1-4ef3-9ef9-e116773da0a7,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:2, IP:nil,URL:1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV: 0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULS X-UUID: 9a087560f02811efaae1fd9735fae912-20250221 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1070376408; Fri, 21 Feb 2025 15:51:04 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Fri, 21 Feb 2025 15:51:03 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Fri, 21 Feb 2025 15:51:02 +0800 From: Friday Yang To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Garmin Chang , Yong Wu CC: Friday Yang , , , , , , Subject: [PATCH v4 1/2] dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188 Date: Fri, 21 Feb 2025 15:50:53 +0800 Message-ID: <20250221075058.14180-2-friday.yang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250221075058.14180-1-friday.yang@mediatek.com> References: <20250221075058.14180-1-friday.yang@mediatek.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On the MediaTek platform, some SMI LARBs are directly connected to the SMI Common, while others are connected to the SMI Sub-Common, which in turn is connected to the SMI Common. The hardware block diagram can be described as follows. SMI-Common(Smart Multimedia Interface Common) | +----------------+------------------+ | | | | | | | | | | | | | | | larb0 SMI-Sub-Common0 SMI-Sub-Common1 | | | | | larb1 larb2 larb3 larb7 larb9 For previous discussion on the direction of the code modifications, please refer to: https://lore.kernel.org/all/CAFGrd9qZhObQXvm2_abqaX83xMLqxjQETB2= wXpobDWU1CnvkA@mail.gmail.com/ https://lore.kernel.org/all/CAPDyKFpokXV2gJDgowbixTvOH_5VL3B5H8ey hP+KJ5Fasm2rFg@mail.gmail.com/ On the MediaTek MT8188 SoC platform, we encountered power-off failures and SMI bus hang issues during camera stress tests. The issue arises because bus glitches are sometimes produced when MTCMOS powers on or off. While this is fairly normal, the software must handle these glitches to avoid mistaking them for transaction signals. What's more, this issue emerged only after the initial upstreaming of this binding. Without these patches, the SMI becomes unstable during camera stress tests. The software solutions can be summarized as follows: 1. Use CLAMP to disable the SMI sub-common port after turning off the LARB CG and before turning off the LARB MTCMOS. 2. Use CLAMP to disable/enable the SMI sub-common port. 3. Implement an AXI reset for SMI LARBs. This patch add '#reset-cells' for the clock controller located in image, camera and IPE subsystems. Signed-off-by: Friday Yang Acked-by: Conor Dooley --- .../bindings/clock/mediatek,mt8188-clock.yaml | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) -- 2.46.0 diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml index 860570320545..2985c8c717d7 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml @@ -57,6 +57,27 @@ required: - reg - '#clock-cells' +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8188-camsys-rawa + - mediatek,mt8188-camsys-rawb + - mediatek,mt8188-camsys-yuva + - mediatek,mt8188-camsys-yuvb + - mediatek,mt8188-imgsys-wpe1 + - mediatek,mt8188-imgsys-wpe2 + - mediatek,mt8188-imgsys-wpe3 + - mediatek,mt8188-imgsys1-dip-nr + - mediatek,mt8188-imgsys1-dip-top + - mediatek,mt8188-ipesys + + then: + required: + - '#reset-cells' + additionalProperties: false examples: