From patchwork Thu Feb 27 12:24:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Madieu X-Patchwork-Id: 13994360 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4D25C1FF1B4; Thu, 27 Feb 2025 12:25:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740659128; cv=none; b=pjkSiv7MRybKQoV7TqOpuhjL0I+c1NYfmxPIygn/M2aGHMUX6Z9UEkDFcx0Ib+vGa2/NRCaFmZMJh7fjaTbCym//P37ToIOxk8n5JDB0o7+vqRLL/BR1aFo7BVPG+ZJPTg1gUWeH5C2EF3Hk319zG3Iq9SJElPt89J8wp+Xd7aU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740659128; c=relaxed/simple; bh=MaJUiVKYlYrGAjIefen+g+xHBtsN3Mh4FfxlKwjJ7F4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=d6XNAdfHKzaBPOcHL23SWXK6XTK79+ZJJ0nzcA2Hzrc0qpM7fEeWZ+JdBDPPwygC5O+P91qjBCPSaON6tPx6NYhx1euEx08DQdSPR1FSV27SIy+cjva2BjWRuYoDSgEZxPebeS9jy5C4iver6DtCwJPwqks/vcpMzx0FKQLkZdU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: c5o7PANlQBGrSvyPSvZHmg== X-CSE-MsgGUID: edZ3QwiJTmGq+7ZZk05JGA== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 27 Feb 2025 21:25:19 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.92.68]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 3A9964004CF4; Thu, 27 Feb 2025 21:25:11 +0900 (JST) From: John Madieu To: john.madieu.xa@bp.renesas.com, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, catalin.marinas@arm.com, will@kernel.org Cc: john.madieu@gmail.com, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, biju.das.jz@bp.renesas.com Subject: [PATCH v2 2/7] clk: renesas: r9a09g047: Add clock and reset signals for the TSU IP Date: Thu, 27 Feb 2025 13:24:38 +0100 Message-ID: <20250227122453.30480-3-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250227122453.30480-1-john.madieu.xa@bp.renesas.com> References: <20250227122453.30480-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add required clocks and resets signals for the TSU IP available on the Renesas RZ/G3E SoC Signed-off-by: John Madieu --- v1 -> v2: no changes drivers/clk/renesas/r9a09g047-cpg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c index 51fd24c20ed5..ada57964c132 100644 --- a/drivers/clk/renesas/r9a09g047-cpg.c +++ b/drivers/clk/renesas/r9a09g047-cpg.c @@ -154,6 +154,8 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { BUS_MSTOP(8, BIT(4))), DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14, BUS_MSTOP(8, BIT(4))), + DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10, + BUS_MSTOP(2, BIT(15))), }; static const struct rzv2h_reset r9a09g047_resets[] __initconst = { @@ -177,6 +179,7 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = { DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ + DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */ }; const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {