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Sun, 30 Mar 2025 14:08:24 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:8249:9390:e853:c628]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d91429c36sm69778175e9.0.2025.03.30.14.08.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Mar 2025 14:08:23 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , Mauro Carvalho Chehab , Kieran Bingham , Stephen Boyd , Philipp Zabel Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-media@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 16/17] drm: renesas: rz-du: mipi_dsi: Add support for LPCLK handling Date: Sun, 30 Mar 2025 22:07:12 +0100 Message-ID: <20250330210717.46080-17-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250330210717.46080-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250330210717.46080-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Introduce the `RZ_MIPI_DSI_HASLPCLK` feature flag in `rzg2l_mipi_dsi_hw_info` to indicate the need for LPCLK configuration. On the RZ/V2H(P) SoC, the LPCLK clock rate influences the required DPHY register configuration, whereas on the RZ/G2L SoC, this clock is not present. To accommodate this difference, add an `lpclk` clock handle in `rzg2l_mipi_dsi` and update the probe function to conditionally acquire LPCLK if the SoC supports it. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c index 2ca725a2ccaf..26ec0f5d065a 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -31,6 +31,7 @@ struct rzg2l_mipi_dsi; #define RZ_MIPI_DSI_16BPP BIT(0) +#define RZ_MIPI_DSI_HASLPCLK BIT(1) struct rzg2l_mipi_dsi_hw_info { int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, unsigned long long hsfreq_mhz); @@ -63,6 +64,7 @@ struct rzg2l_mipi_dsi { struct drm_bridge *next_bridge; struct clk *vclk; + struct clk *lpclk; enum mipi_dsi_pixel_format format; unsigned int num_data_lanes; @@ -792,6 +794,12 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) if (IS_ERR(dsi->vclk)) return PTR_ERR(dsi->vclk); + if (dsi->info->features & RZ_MIPI_DSI_HASLPCLK) { + dsi->lpclk = devm_clk_get(dsi->dev, "lpclk"); + if (IS_ERR(dsi->lpclk)) + return PTR_ERR(dsi->lpclk); + } + if (dsi->info->has_dphy_rstc) { dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst"); if (IS_ERR(dsi->rstc))