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Wed, 2 Apr 2025 13:12:33 +0000 From: Tommaso Merciai To: tomm.merciai@gmail.com Cc: linux-renesas-soc@vger.kernel.org, biju.das.jz@bp.renesas.com, Tommaso Merciai , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] clk: renesas: r9a09g047: Add clock and reset entries for GE3D Date: Wed, 2 Apr 2025 15:11:38 +0200 Message-ID: <20250402131142.1270701-2-tommaso.merciai.xr@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250402131142.1270701-1-tommaso.merciai.xr@bp.renesas.com> References: <20250402131142.1270701-1-tommaso.merciai.xr@bp.renesas.com> X-ClientProxiedBy: FR4P281CA0173.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:b7::16) To OS9PR01MB13950.jpnprd01.prod.outlook.com (2603:1096:604:35e::5) Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OS9PR01MB13950:EE_|TYCPR01MB6688:EE_ X-MS-Office365-Filtering-Correlation-Id: c5c6145d-3daf-4993-3b55-08dd71e80778 X-LD-Processed: 53d82571-da19-47e4-9cb4-625a166a4a2a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|52116014|1800799024|366016|38350700014; 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Signed-off-by: Tommaso Merciai --- drivers/clk/renesas/r9a09g047-cpg.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c index e9cf4342d0cfb..2aa1e0aa4d36d 100644 --- a/drivers/clk/renesas/r9a09g047-cpg.c +++ b/drivers/clk/renesas/r9a09g047-cpg.c @@ -41,6 +41,7 @@ enum clk_ids { CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_DIV16, CLK_PLLVDO_CRU0, + CLK_PLLVDO_GPU, /* Module Clocks */ MOD_CLK_BASE, @@ -96,6 +97,7 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16), DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4), + DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtable_2_64), /* Core Clocks */ DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1), @@ -185,6 +187,12 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { BUS_MSTOP(9, BIT(4))), DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10, BUS_MSTOP(2, BIT(15))), + DEF_MOD("ge3d_clk", CLK_PLLVDO_GPU, 15, 0, 7, 16, + BUS_MSTOP(3, BIT(4))), + DEF_MOD("ge3d_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17, + BUS_MSTOP(3, BIT(4))), + DEF_MOD("ge3d_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18, + BUS_MSTOP(3, BIT(4))), }; static const struct rzv2h_reset r9a09g047_resets[] __initconst = { @@ -214,6 +222,9 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = { DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */ DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */ DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */ + DEF_RST(13, 13, 6, 14), /* GE3D_0_RESETN */ + DEF_RST(13, 14, 6, 15), /* GE3D_0_AXI_RESETN */ + DEF_RST(13, 15, 6, 16), /* GE3D_0_ACE_RESETN */ }; const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {