| Message ID | 54f8c5ce9c84265437734943f68e3ee4c2458bd5.1574922435.git.shubhrajyoti.datta@xilinx.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | clk: clk-wizard: clock-wizard: Driver updates | expand |
On Thu, Nov 28, 2019 at 12:06:08PM +0530, shubhrajyoti.datta@gmail.com wrote: > From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > > Add the devicetree binding for the xilinx clocking wizard. > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > --- > .../bindings/clock/xlnx,clocking-wizard.txt | 32 ++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.txt New bindings should be in DT schema format. > > diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.txt b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.txt > new file mode 100644 > index 0000000..aedac84 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.txt > @@ -0,0 +1,32 @@ > +Binding for Xilinx Clocking Wizard IP Core > + > +This binding uses the common clock binding[1]. Details about the devices can be > +found in the product guide[2]. > + > +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt > +[2] Clocking Wizard Product Guide > +http://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1/pg065-clk-wiz.pdf > + > +Required properties: > + - compatible: Must be 'xlnx,clocking-wizard' That's not very specific. Is there only 1 version of this h/w? > + - #clock-cells: Number of cells in a clock specifier. Should be 1 > + - reg: Base and size of the cores register space > + - clocks: Handle to input clock > + - clock-names: Tuple containing 'clk_in1' and 's_axi_aclk' > + - clock-output-names: Names for the output clocks You have to define the values. > + > +Optional properties: > + - speed-grade: Speed grade of the device (valid values are 1..3) > + > +Example: > + clock-generator@40040000 { > + #clock-cells = <1>; > + reg = <0x40040000 0x1000>; > + compatible = "xlnx,clocking-wizard"; > + speed-grade = <1>; > + clock-names = "clk_in1", "s_axi_aclk"; > + clocks = <&clkc 15>, <&clkc 15>; > + clock-output-names = "clk_out0", "clk_out1", "clk_out2", > + "clk_out3", "clk_out4", "clk_out5", > + "clk_out6", "clk_out7"; Don't really need this to be in DT given all the names are the same except for the index. Rob
diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.txt b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.txt new file mode 100644 index 0000000..aedac84 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.txt @@ -0,0 +1,32 @@ +Binding for Xilinx Clocking Wizard IP Core + +This binding uses the common clock binding[1]. Details about the devices can be +found in the product guide[2]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Clocking Wizard Product Guide +http://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1/pg065-clk-wiz.pdf + +Required properties: + - compatible: Must be 'xlnx,clocking-wizard' + - #clock-cells: Number of cells in a clock specifier. Should be 1 + - reg: Base and size of the cores register space + - clocks: Handle to input clock + - clock-names: Tuple containing 'clk_in1' and 's_axi_aclk' + - clock-output-names: Names for the output clocks + +Optional properties: + - speed-grade: Speed grade of the device (valid values are 1..3) + +Example: + clock-generator@40040000 { + #clock-cells = <1>; + reg = <0x40040000 0x1000>; + compatible = "xlnx,clocking-wizard"; + speed-grade = <1>; + clock-names = "clk_in1", "s_axi_aclk"; + clocks = <&clkc 15>, <&clkc 15>; + clock-output-names = "clk_out0", "clk_out1", "clk_out2", + "clk_out3", "clk_out4", "clk_out5", + "clk_out6", "clk_out7"; + };