From patchwork Wed May 17 07:40:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 9730129 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 22018602DB for ; Wed, 17 May 2017 07:41:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 13B5E286E5 for ; Wed, 17 May 2017 07:41:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0827E28700; Wed, 17 May 2017 07:41:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AA974286E5 for ; Wed, 17 May 2017 07:41:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753633AbdEQHlQ (ORCPT ); Wed, 17 May 2017 03:41:16 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:47708 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753259AbdEQHlL (ORCPT ); Wed, 17 May 2017 03:41:11 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 0822F20850; Wed, 17 May 2017 09:41:09 +0200 (CEST) Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id D28C42085A; Wed, 17 May 2017 09:40:58 +0200 (CEST) From: Maxime Ripard To: Chen-Yu Tsai , Maxime Ripard , Mike Turquette , Stephen Boyd Cc: Daniel Vetter , David Airlie , dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni Subject: [PATCH v3 13/21] drm/sun4i: tcon: Change vertical total size computation inconsistency Date: Wed, 17 May 2017 09:40:42 +0200 Message-Id: <5f1e156ed132defe5ec58b4e2a97764d73eba5f3.1495006350.git-series.maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Both TCON channels need to have the resolution doubled, since the size the hardware is going to use is whatever we put in the register divided by two. However, we handle it differently for the two channels: in the channel 0, our register access macro does the multiplication of the value passed as paremeter, while in the channel 1, the macro doesn't do this, and we need to do it before calling it. Make this consistent by aligning the channel 0 with the channel 1 behaviour. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 2 +- drivers/gpu/drm/sun4i/sun4i_tcon.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index 931dd374552e..62e254aedb57 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -194,7 +194,7 @@ void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon, /* Set vertical display timings */ regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, - SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal) | + SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) | SUN4I_TCON0_BASIC2_V_BACKPORCH(bp)); /* Set Hsync and Vsync length */ diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h index f60e0b4c6db8..e3c50ecdcd04 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h @@ -52,7 +52,7 @@ #define SUN4I_TCON0_BASIC1_H_BACKPORCH(bp) (((bp) - 1) & 0xfff) #define SUN4I_TCON0_BASIC2_REG 0x50 -#define SUN4I_TCON0_BASIC2_V_TOTAL(total) ((((total) * 2) & 0x1fff) << 16) +#define SUN4I_TCON0_BASIC2_V_TOTAL(total) (((total) & 0x1fff) << 16) #define SUN4I_TCON0_BASIC2_V_BACKPORCH(bp) (((bp) - 1) & 0xfff) #define SUN4I_TCON0_BASIC3_REG 0x54