From patchwork Thu Mar 30 07:18:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 9653091 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0806D60349 for ; Thu, 30 Mar 2017 07:19:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EDEA128509 for ; Thu, 30 Mar 2017 07:19:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E28E928571; Thu, 30 Mar 2017 07:19:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7644F28509 for ; Thu, 30 Mar 2017 07:19:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932731AbdC3HTA (ORCPT ); Thu, 30 Mar 2017 03:19:00 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:24581 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755134AbdC3HSy (ORCPT ); Thu, 30 Mar 2017 03:18:54 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2U7INso012094; Thu, 30 Mar 2017 02:18:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1490858303; bh=Lcfvm772NQJoM3WyIM5WgYo95qg5DOHgl+abcMeHfpQ=; h=Subject:To:References:CC:From:Date:In-Reply-To; b=WIxMnKAFp2C7D/SD5UXnPndL1hb+HVlveR5L2jHjqaFe2cLLiOfmwgCFWIVGjorCm 9Z4k3deMFS9wfLpaWLqKgAZybMkrypjdjL13poEtsiV66gHc2I+zjvKGYrbXnIBNMk qVEuoftMKyuCndkgbuXVHuW8W6zY8pGcX/NiY2ik= Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2U7IN3u006997; Thu, 30 Mar 2017 02:18:23 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Thu, 30 Mar 2017 02:18:22 -0500 Received: from [172.22.5.0] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2U7IHtk001172; Thu, 30 Mar 2017 02:18:18 -0500 Subject: Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks To: Tony Lindgren References: <1489741781-12816-1-git-send-email-t-kristo@ti.com> <20170317152536.GT20572@atomide.com> <94d20a17-5072-ffab-3529-4bbb14327a10@ti.com> <20170323010057.GI10760@atomide.com> <20170323170210.GL10760@atomide.com> CC: , , , , From: Tero Kristo Message-ID: <8648f054-cf04-41df-20f3-82e0d63feefa@ti.com> Date: Thu, 30 Mar 2017 10:18:14 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.7.0 MIME-Version: 1.0 In-Reply-To: <20170323170210.GL10760@atomide.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 23/03/17 19:02, Tony Lindgren wrote: > * Tony Lindgren [170322 18:03]: >> * Tero Kristo [170317 14:39]: >>> On 17/03/17 17:25, Tony Lindgren wrote: >>>> * Tero Kristo [170317 02:12]: >>>>> Any additional testing on omap4 welcome as this series basically >>>>> tweaks every possible peripheral clock on the SoC. >>>> >>>> Without the last patch in this series, booting fails for me: >>>> >>>> [ 5.074890] l4_per_cm:clk:0120:0: failed to disable >>>> [ 5.085113] l4_per_cm:clk:0128:0: failed to disable >>>> >>>> Care to check that booting keeps working for each patch in the >>>> series to avoid breaking git bisect for booting? >>> >>> Hmm, I think patch 8+9 need to be squashed then. I can double check this >>> next week though. >> >> Also looks like with this set merged HDMI stops working on >> omap4 with: >> >> HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1 > > Forgot to mention that's with omapdrm with encoder-tpd12s015 and > encoder-tfp410 modules loaded to get HDMI working. Here's more verbose > dmesg output in case that provides more clues: > > [ 91.042877] omapdss HDMICORE error: operation stopped when reading edid > [ 91.078308] [drm] Enabling DMM ywrap scrolling > [ 91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1 > [ 91.107879] omapdss HDMI error: failed to power on device > [ 91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5 > [ 91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)! > [ 91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)! > [ 91.620300] Console: switching to colour frame buffer device 128x48 > [ 91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device > [ 91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0 > [ 92.818054] omapdss HDMICORE error: operation stopped when reading edid > [ 93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)! > [ 93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)! > > Regards, > > Tony > Can you try with this additional hwmod data tweak in place? Apply this on top of the existing series. =========== From 8ba1829078ea9a7417a34564fde8a30c9bdeb273 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 30 Mar 2017 10:09:59 +0300 Subject: [PATCH] ARM: OMAP4: hwmod_data: add opt clks for dss_hdmi and dss_venc These extra optional clocks are required as main clock for these modules are going to be routed to the main module clock. Otherwise, the hdmi / tv clocks are not going to be enabled during usage, leading to failure. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index dad871a..2a9d092 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -775,6 +775,7 @@ static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { { .role = "sys_clk", .clk = "dss_sys_clk" }, + { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, }; static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { @@ -858,6 +859,10 @@ }; /* dss_venc */ +static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { + { .role = "tv_clk", .clk = "dss_tv_clk" }, +}; + static struct omap_hwmod omap44xx_dss_venc_hwmod = { .name = "dss_venc", .class = &omap44xx_venc_hwmod_class, @@ -870,6 +875,8 @@ }, }, .parent_hwmod = &omap44xx_dss_hwmod, + .opt_clks = dss_venc_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), }; /*