From patchwork Thu Jun 1 14:55:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 9759805 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F1A3A602BC for ; Thu, 1 Jun 2017 14:59:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E1A1827FA8 for ; Thu, 1 Jun 2017 14:59:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D631C283BF; Thu, 1 Jun 2017 14:59:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 80AB727FA8 for ; Thu, 1 Jun 2017 14:59:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751129AbdFAO6w (ORCPT ); Thu, 1 Jun 2017 10:58:52 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:41238 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751180AbdFAOz4 (ORCPT ); Thu, 1 Jun 2017 10:55:56 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 4A2432081C; Thu, 1 Jun 2017 16:55:53 +0200 (CEST) Received: from localhost (83.146.29.93.rev.sfr.net [93.29.146.83]) by mail.free-electrons.com (Postfix) with ESMTPSA id 20CDA20713; Thu, 1 Jun 2017 16:55:53 +0200 (CEST) From: Gregory CLEMENT To: Stephen Boyd , Mike Turquette , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Gregory CLEMENT , Thomas Petazzoni , linux-arm-kernel@lists.infradead.org, Rob Herring , devicetree@vger.kernel.org, Nadav Haklai , Kostya Porotchkin , Neta Zur Hershkovits , Marcin Wojtas , Omri Itach , Shadi Ammouri Subject: [PATCH v3 4/9] dt-bindings: cp110: introduce a new binding Date: Thu, 1 Jun 2017 16:55:37 +0200 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch updates the documentation according to the change made in the patch "pinctrl: dt-bindings: cp110: introduce a new binding". Acked-by: Rob Herring Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt index dbd0a38ca580..e97cc2d73e2e 100644 --- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt +++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt @@ -7,6 +7,13 @@ Controller 0 and System Controller 1. This Device Tree binding allows to describe the first system controller, which provides registers to configure various aspects of the SoC. +For the top level node: + - compatible: must be: "syscon", "simple-mfd"; + - reg: register area of the CP110 system controller 0 + +Clocks: +------- + The Device Tree node representing this System Controller 0 provides a number of clocks: @@ -56,14 +63,17 @@ The following clocks are available: Required properties: - compatible: must be: - "marvell,cp110-system-controller0", "syscon"; - - reg: register area of the CP110 system controller 0 + "marvell,cp110-clock" - #clock-cells: must be set to 2 Example: cpm_syscon0: system-controller@440000 { - compatible = "marvell,cp110-system-controller0", "syscon"; + compatible = "syscon", "simple-mfd"; reg = <0x440000 0x1000>; - #clock-cells = <2>; + + cpm_clk: clock { + compatible = "marvell,cp110-clock"; + #clock-cells = <2>; + }; };