From patchwork Tue Jan 22 19:57:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 10776197 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5C2361390 for ; Tue, 22 Jan 2019 19:57:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4C3942B95E for ; Tue, 22 Jan 2019 19:57:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 405272B960; Tue, 22 Jan 2019 19:57:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BC0D42B96A for ; Tue, 22 Jan 2019 19:57:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726015AbfAVT5n (ORCPT ); Tue, 22 Jan 2019 14:57:43 -0500 Received: from mail-lj1-f196.google.com ([209.85.208.196]:39357 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726095AbfAVT5n (ORCPT ); Tue, 22 Jan 2019 14:57:43 -0500 Received: by mail-lj1-f196.google.com with SMTP id t9-v6so21768890ljh.6 for ; Tue, 22 Jan 2019 11:57:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=subject:from:to:references:organization:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=y5pD8IiGs3MGHd/hieqN/F+NJHTyJgePEHoUTjzBTFY=; b=JN3V1nIT8+QXSF09xw/u75brDWFUYn65iZ8LRHf6efZNjTCndk+eKQ8khHhIzXrrzc cistc6NBaeSMasq0PAad4rW49F++iNTqEafXy8TW469bBNRJUKOYAM0C4tN8BwOEmcec CGA3ASZ9nx2gHX6s9TvU4/OWI96+gmKSIjyx/Z7O6pUhfoszRHXtM3XZKd9MCeQ82OaN +ChlT+N6Kft4H2s+B+lLLEul1jVJuLbw+pEGliWxaFiCQQVM1CD49YQ1syjEaSM6wfFm M1m68/aQP/SI84zfnd4AAy4Y2aZXjl3Kv9kay+tlNOX6Ku5FGETLq15OoPp+Oij0+hyi InoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:from:to:references:organization :message-id:date:user-agent:mime-version:in-reply-to :content-language:content-transfer-encoding; bh=y5pD8IiGs3MGHd/hieqN/F+NJHTyJgePEHoUTjzBTFY=; b=l8f6IlwV1svJR8u2/tNX5HEeKLh/61yxN8QO+/VQnXM0nf9536XsQh5+k7stkiPijS OrInr/oB9ZeSHX+S+8lAdW9/Zkd2XUYTgfxbwT9GkE1lVct/YEEUCkhEmUZRKF/QpKD9 lKeVYFmP2TUciCG8P5CpwURJgezMIsoIycun1H5tHT6p5QeWKZEjaQ7G4CcNgiuWnEXx fKOlUc1RUtLFu3CelbhTmKU87+s6h8Moii4Ch9OgqDcsIhluYHgnYqEWzV5xjk8BmETp 33gz6rRa9udIko5mfU4jLYRoDZlaAjJfDJj3W2prvFvZIpuOEsy5sok4B9ZJtWadd+xI OX1g== X-Gm-Message-State: AJcUukfUWjpzHef6JnoASxSThfqGXcYaoubRXvkEEmaDY6b4BgyLPu1G rgfFvtJsJtaLDExGXihbZOMmcXjXyIc= X-Google-Smtp-Source: ALg8bN5XJtshftwEDXSVFyBk3gLXsVOjty93l0wMCG+VkX5D8hhA6fb3lQoZHkwCu2DfNTl8S3Fy+Q== X-Received: by 2002:a2e:83d7:: with SMTP id s23-v6mr23760996ljh.139.1548187059902; Tue, 22 Jan 2019 11:57:39 -0800 (PST) Received: from wasted.cogentembedded.com ([31.173.82.69]) by smtp.gmail.com with ESMTPSA id k20sm150788lfe.3.2019.01.22.11.57.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 22 Jan 2019 11:57:39 -0800 (PST) Subject: [PATCH v3 1/4] clk: renesas: rcar-gen3-cpg: factor out cpg_reg_modify() From: Sergei Shtylyov To: linux-renesas-soc@vger.kernel.org, Michael Turquette , Stephen Boyd , Geert Uytterhoeven , linux-clk@vger.kernel.org References: Organization: Cogent Embedded Message-ID: Date: Tue, 22 Jan 2019 22:57:38 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-MW Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There's quite often repeated sequence of a CPG register read-modify-write, so it seems worth factoring it out into a function -- this saves 68 bytes of the object code (AArch64 gcc 4.8.5) and simplifies protecting all such sequences with a spinlock in the next patch... Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven --- Changes in version 3: - refreshed the patch; - added Geert's tag. Changes in version 2: - moved the readl() call from the initializer in cpg_reg_modify(); - adjusted the patch description. drivers/clk/renesas/rcar-gen3-cpg.c | 38 ++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 18 deletions(-) Index: renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c =================================================================== --- renesas-drivers.orig/drivers/clk/renesas/rcar-gen3-cpg.c +++ renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c @@ -30,6 +30,16 @@ #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */ +static void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set) +{ + u32 val; + + val = readl(reg); + val &= ~clear; + val |= set; + writel(val, reg); +}; + struct cpg_simple_notifier { struct notifier_block nb; void __iomem *reg; @@ -118,7 +128,6 @@ static int cpg_z_clk_set_rate(struct clk struct cpg_z_clk *zclk = to_z_clk(hw); unsigned int mult; unsigned int i; - u32 val, kick; /* Factor of 2 is for fixed divider */ mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate); @@ -127,17 +136,14 @@ static int cpg_z_clk_set_rate(struct clk if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) return -EBUSY; - val = readl(zclk->reg) & ~zclk->mask; - val |= ((32 - mult) << __ffs(zclk->mask)) & zclk->mask; - writel(val, zclk->reg); + cpg_reg_modify(zclk->reg, zclk->mask, + ((32 - mult) << __ffs(zclk->mask)) & zclk->mask); /* * Set KICK bit in FRQCRB to update hardware setting and wait for * clock change completion. */ - kick = readl(zclk->kick_reg); - kick |= CPG_FRQCRB_KICK; - writel(kick, zclk->kick_reg); + cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK); /* * Note: There is no HW information about the worst case latency. @@ -266,12 +272,10 @@ static const struct sd_div_table cpg_sd_ static int cpg_sd_clock_enable(struct clk_hw *hw) { struct sd_clock *clock = to_sd_clock(hw); - u32 val = readl(clock->csn.reg); - - val &= ~(CPG_SD_STP_MASK); - val |= clock->div_table[clock->cur_div_idx].val & CPG_SD_STP_MASK; - writel(val, clock->csn.reg); + cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK, + clock->div_table[clock->cur_div_idx].val & + CPG_SD_STP_MASK); return 0; } @@ -280,7 +284,7 @@ static void cpg_sd_clock_disable(struct { struct sd_clock *clock = to_sd_clock(hw); - writel(readl(clock->csn.reg) | CPG_SD_STP_MASK, clock->csn.reg); + cpg_reg_modify(clock->csn.reg, 0, CPG_SD_STP_MASK); } static int cpg_sd_clock_is_enabled(struct clk_hw *hw) @@ -327,7 +331,6 @@ static int cpg_sd_clock_set_rate(struct { struct sd_clock *clock = to_sd_clock(hw); unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate); - u32 val; unsigned int i; for (i = 0; i < clock->div_num; i++) @@ -339,10 +342,9 @@ static int cpg_sd_clock_set_rate(struct clock->cur_div_idx = i; - val = readl(clock->csn.reg); - val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK); - val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK); - writel(val, clock->csn.reg); + cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK | CPG_SD_FC_MASK, + clock->div_table[i].val & + (CPG_SD_STP_MASK | CPG_SD_FC_MASK)); return 0; }