From patchwork Wed May 31 14:07:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 9757263 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 66EB2603F7 for ; Wed, 31 May 2017 14:09:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 57D0B201BD for ; Wed, 31 May 2017 14:09:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4CA48204BD; Wed, 31 May 2017 14:09:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ECCDC203B9 for ; Wed, 31 May 2017 14:09:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751522AbdEaOJc (ORCPT ); Wed, 31 May 2017 10:09:32 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:40962 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751647AbdEaOHp (ORCPT ); Wed, 31 May 2017 10:07:45 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 71F1D20F21; Wed, 31 May 2017 16:07:42 +0200 (CEST) Received: from localhost (83.146.29.93.rev.sfr.net [93.29.146.83]) by mail.free-electrons.com (Postfix) with ESMTPSA id 47D3D20F26; Wed, 31 May 2017 16:07:32 +0200 (CEST) From: Gregory CLEMENT To: Stephen Boyd , Mike Turquette , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Gregory CLEMENT , Thomas Petazzoni , linux-arm-kernel@lists.infradead.org, Rob Herring , devicetree@vger.kernel.org, Nadav Haklai , Kostya Porotchkin , Neta Zur Hershkovits , Marcin Wojtas , Omri Itach , Shadi Ammouri Subject: [PATCH v2 7/7] arm64: dts: marvell: use new binding for the system controller on ap806 Date: Wed, 31 May 2017 16:07:28 +0200 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The new binding for the system controller on ap806 moved the clock into a subnode. This preliminary step will allow to add gpio and pinctrl subnodes Reviewed-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi index 0c25ec62a2a3..205037e3e7dc 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi @@ -193,7 +193,7 @@ #size-cells = <0>; cell-index = <0>; interrupts = ; - clocks = <&ap_syscon 3>; + clocks = <&ap_clk 3>; status = "disabled"; }; @@ -204,7 +204,7 @@ #size-cells = <0>; interrupts = ; timeout-ms = <1000>; - clocks = <&ap_syscon 3>; + clocks = <&ap_clk 3>; status = "disabled"; }; @@ -214,7 +214,7 @@ reg-shift = <2>; interrupts = ; reg-io-width = <1>; - clocks = <&ap_syscon 3>; + clocks = <&ap_clk 3>; status = "disabled"; }; @@ -224,7 +224,7 @@ reg-shift = <2>; interrupts = ; reg-io-width = <1>; - clocks = <&ap_syscon 3>; + clocks = <&ap_clk 3>; status = "disabled"; }; @@ -234,17 +234,20 @@ reg = <0x6e0000 0x300>; interrupts = ; clock-names = "core"; - clocks = <&ap_syscon 4>; + clocks = <&ap_clk 4>; dma-coherent; marvell,xenon-phy-slow-mode; status = "disabled"; }; ap_syscon: system-controller@6f4000 { - compatible = "marvell,ap806-system-controller", - "syscon"; - #clock-cells = <1>; + compatible = "syscon", "simple-mfd"; reg = <0x6f4000 0x1000>; + + ap_clk: clock { + compatible = "marvell,ap806-clock"; + #clock-cells = <1>; + }; }; }; };