From patchwork Tue May 12 04:08:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhangfei Gao X-Patchwork-Id: 11542037 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7FF5F15E6 for ; Tue, 12 May 2020 04:09:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 672A820769 for ; Tue, 12 May 2020 04:09:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="rFjrz9rD" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725554AbgELEJL (ORCPT ); Tue, 12 May 2020 00:09:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725982AbgELEJL (ORCPT ); Tue, 12 May 2020 00:09:11 -0400 Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D7463C061A0E for ; Mon, 11 May 2020 21:09:09 -0700 (PDT) Received: by mail-pf1-x441.google.com with SMTP id 18so5738148pfx.6 for ; Mon, 11 May 2020 21:09:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=yP6D/ixJy1go9I3dKKTs64wSH22i2lwmmxRms2M5Log=; b=rFjrz9rDOYj5kTHRA9iW5hkbpiDEvFt+HIsb9wikLbrAcUSBldbXdKbYpt7EC1eJDu vRHSLfztu+FL84B8qSEaDPj8TR5zF5dkvnWMEeUDhSnZ+o/ZnUI+g+/glbL5QZ2l26Ub Kf+pFuNVkyX/xujz123lwbFV/+v26ivFpNzRv/JeytkerLige4bEVIcCMmxeDtRlBM8m kZUZMWJ0WGaufznZ5GG/vWLyEE2dRwH2mFe4SPaUAVgmMAn5sVG2MoyfJcODZO8umdGA 2Dmm/WMEM2kcg5U7AGkly7XNwyB+33DyaTkJex9y2wstyBJ+GIEa26FYtJloj3tV8CIr oPBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=yP6D/ixJy1go9I3dKKTs64wSH22i2lwmmxRms2M5Log=; b=dcaTof911CIZF5QKkzU83pjgLBUduRmEclT3J6FP1dohzaeQEtfmewZXgtAHbDKcte rzyb0IDqK6OCpuGkuCl2gNPksI6XaHPMcEqd8c4U/ejA3f97hdN/6E3NZ9hs0pTR47AR EBEfMoGmEXjIuDc8yKh10nZwoqeKiHJo1k/ZBDs7WXGrF847d2hdbfLUK7QHRgkb36Vd BJGV8BI5ecCxjPuTZd+EYx5ywEzKnBK0i24fnYrdxIjYrpUxj56g+gXLaUTx0CqhYtzK MCyqQIfGofHQFaJyWxCVxNrjqQ1XzANG7kfM9TuaYRbhoXj13Ij+cpjZ+LVpZG6YMhVV yASw== X-Gm-Message-State: AOAM532rb/QuXyxWV++aOWHjKB25tGL2fQmVR7fkErSBU4eWDtVSaxbb LtSYVfKjymhSBDemVpV6K9yAOw== X-Google-Smtp-Source: ABdhPJwR/mT3M4ET0gUnmGWVdzywReAuxXeomuc5BK5uwflbMkhGQbsFgUJAeMnqFKRm6B3nbWRNqQ== X-Received: by 2002:a63:3ec4:: with SMTP id l187mr8207696pga.358.1589256549383; Mon, 11 May 2020 21:09:09 -0700 (PDT) Received: from localhost.localdomain ([240e:362:443:6f00:91af:f25c:441c:7ba4]) by smtp.gmail.com with ESMTPSA id e4sm9471527pge.45.2020.05.11.21.08.56 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 May 2020 21:09:08 -0700 (PDT) From: Zhangfei Gao To: Joerg Roedel , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , "Rafael J. Wysocki" , Len Brown , jean-philippe , Greg Kroah-Hartman , Herbert Xu , kenneth-lee-2012@foxmail.com, Wangzhou Cc: linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, iommu@lists.linux-foundation.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Zhangfei Gao Subject: [PATCH 0/2] Let pci_fixup_final access iommu_fwnode Date: Tue, 12 May 2020 12:08:29 +0800 Message-Id: <1589256511-12446-1-git-send-email-zhangfei.gao@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Some platform devices appear as PCI but are actually on the AMBA bus, and they need fixup in drivers/pci/quirks.c handling iommu_fwnode. So calling pci_fixup_final after iommu_fwnode is allocated. For example: Hisilicon platform device need fixup in drivers/pci/quirks.c +static void quirk_huawei_pcie_sva(struct pci_dev *pdev) +{ + struct iommu_fwspec *fwspec; + + pdev->eetlp_prefix_path = 1; + fwspec = dev_iommu_fwspec_get(&pdev->dev); + if (fwspec) + fwspec->can_stall = 1; +} + +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva); Zhangfei Gao (2): iommu/of: Let pci_fixup_final access iommu_fwnode ACPI/IORT: Let pci_fixup_final access iommu_fwnode drivers/acpi/arm64/iort.c | 1 + drivers/iommu/of_iommu.c | 1 + 2 files changed, 2 insertions(+)