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Wed, 3 Apr 2024 03:00:58 -0700 Received: from BUILDSERVER-IO-L4T.nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Wed, 3 Apr 2024 03:00:53 -0700 From: Akhil R To: , , , , , , , , , , , , , , , , , CC: Akhil R Subject: [PATCH v7 0/5] Add Tegra Security Engine driver Date: Wed, 3 Apr 2024 15:30:34 +0530 Message-ID: <20240403100039.33146-1-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.43.2 Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB73:EE_|DS0PR12MB9324:EE_ X-MS-Office365-Filtering-Correlation-Id: 83cfa25b-9f7f-4f7f-b32c-08dc53c5011f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: yvfagaMqM9mF8xvya+XBkmROp9r7ZRUw5gaHiOFyerrfTu6avQtwA7h+v7ZPTvBDgMk7XBE95gM8sI1wWbQo9hfM+18hQF2TQSX/LcEklP7n+XJITKgTYvbaUO4/t1LziLbxg2+6Nbpt52CYCLTTt4/TQ2SP47YC5rZFoPoKYKBk5uFAM/RO0W+woA3/wWQZxEY+xIdQxKvfUTTWB6pr0vM5BUrpSlXTnb9G9yMGvdRX2XvlEBYFrD4xNpNTmWkSLK3Zc8rcIKBoXp4KSUXbZjQyj+OqVyXcIJm9zn4cwM67UfUWk0vsIWpAIifR4PpJPcxKlHCRLiRxk8c+m10hwdyWsQE/aznL1tMY9VTsK8v/7t10TxWx7W0eEYwCp1cUFweITP0MRAzGe8kVHwVwCWlUAXw/wE+md/3dYl6ixi89wmsBj14iVohiRZXWgK7ciK8gN8r6/iVxl6rl/c4iZEMtMVNcSVzLwjjum2B7/EUHdx6b0nzjjOENHu+V7NiK8WmX9x5XPVjYFKsb8YzAEfm7V6xj7/X25cCqvBp/aU8MAH1oc3FcRfYA9cN87gPDXxq6nboMFeQhgEloynJ4VY12qI8ADxG7yLOa5ZVnnnP8M/LtovM6FVHGYFlVCfzJhtcbBq+6tbC5hTYRp0Gba24pemeslMsoCXZQVIdlIcTfhfoPrAlXaqT0hRHpSgRDJQjUrJY0Xf0XvV9wr+mSPAk10+JBwMR+0/HfyOExPuc23KGjD6rqGhQBcx38uO7T9bFWjXzPlAE8AKLcAVUHwg== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(36860700004)(7416005)(376005)(82310400014)(1800799015)(921011);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Apr 2024 10:01:17.0254 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83cfa25b-9f7f-4f7f-b32c-08dc53c5011f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB73.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9324 Add support for Tegra Security Engine which can accelerates various crypto algorithms. The Engine has two separate instances within for AES and HASH algorithms respectively. The driver registers two crypto engines - one for AES and another for HASH algorithms and these operate independently and both uses the host1x bus. Additionally, it provides hardware-assisted key protection for up to 15 symmetric keys which it can use for the cipher operations. v6->v7: * Move fallback_tfm and fallback_req to end of struct * Set reqsize and statesize based on fallback_tfm * Remove ofb(aes) v5->v6: * Move copy/pase of intermediate results in export()/import() to 'update()' callback for CMAC as well. * Check for rctx size when using fallback alg. * Updated blocksizes to align with generic implementation * Combined GCM and CCM init into aead_cra_init * Updates to handle invalid cases better * Reduce log levels for invalid cases to dev_dbg v4->v5: * Move copy/paste of intermediate results in export()/import() to 'update()' callback v3->v4: * Remove unused header in bindings doc. * Update commit message in host1x change. * Fix test bot warning. v2->v3: * Update compatible in driver and device trees. * Remove extra new lines and symbols in binding doc. v1->v2: * Update probe errors with 'dev_err_probe'. * Clean up function prototypes and redundant prints. * Remove readl/writel wrappers. * Fix test bot warnings. Akhil R (5): dt-bindings: crypto: Add Tegra Security Engine gpu: host1x: Add Tegra SE to SID table crypto: tegra: Add Tegra Security Engine driver arm64: defconfig: Enable Tegra Security Engine arm64: tegra: Add Tegra Security Engine DT nodes .../crypto/nvidia,tegra234-se-aes.yaml | 52 + .../crypto/nvidia,tegra234-se-hash.yaml | 52 + MAINTAINERS | 5 + arch/arm64/boot/dts/nvidia/tegra234.dtsi | 16 + arch/arm64/configs/defconfig | 1 + drivers/crypto/Kconfig | 8 + drivers/crypto/Makefile | 1 + drivers/crypto/tegra/Makefile | 9 + drivers/crypto/tegra/tegra-se-aes.c | 1933 +++++++++++++++++ drivers/crypto/tegra/tegra-se-hash.c | 1060 +++++++++ drivers/crypto/tegra/tegra-se-key.c | 156 ++ drivers/crypto/tegra/tegra-se-main.c | 439 ++++ drivers/crypto/tegra/tegra-se.h | 560 +++++ drivers/gpu/host1x/dev.c | 24 + 14 files changed, 4316 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-aes.yaml create mode 100644 Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-hash.yaml create mode 100644 drivers/crypto/tegra/Makefile create mode 100644 drivers/crypto/tegra/tegra-se-aes.c create mode 100644 drivers/crypto/tegra/tegra-se-hash.c create mode 100644 drivers/crypto/tegra/tegra-se-key.c create mode 100644 drivers/crypto/tegra/tegra-se-main.c create mode 100644 drivers/crypto/tegra/tegra-se.h