| Message ID | 20171212112020.2269-1-larper@axis.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Herbert Xu |
| Headers | show |
On Tue, Dec 12, 2017 at 12:20:20PM +0100, Lars Persson wrote: > The IV size should not include the 32 bit counter. Because we had the > IV size set as 16 the transform only worked when the IV input was zero > padded. > > Fixes: a21eb94fc4d3 ("crypto: axis - add ARTPEC-6/7 crypto accelerator driver") > Signed-off-by: Lars Persson <larper@axis.com> > --- > drivers/crypto/axis/artpec6_crypto.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/crypto/axis/artpec6_crypto.c b/drivers/crypto/axis/artpec6_crypto.c > index 456278440863..4de1996120e7 100644 > --- a/drivers/crypto/axis/artpec6_crypto.c > +++ b/drivers/crypto/axis/artpec6_crypto.c > @@ -1934,7 +1934,7 @@ static int artpec6_crypto_prepare_aead(struct aead_request *areq) > > memcpy(req_ctx->hw_ctx.J0, areq->iv, crypto_aead_ivsize(cipher)); > // The HW omits the initial increment of the counter field. > - crypto_inc(req_ctx->hw_ctx.J0+12, 4); > + memcpy(req_ctx->hw_ctx.J0+12, "\x00\x00\x00\x01", 4); > > ret = artpec6_crypto_setup_out_descr(common, &req_ctx->hw_ctx, > sizeof(struct artpec6_crypto_aead_hw_ctx), false, false); > @@ -2956,7 +2956,7 @@ static struct aead_alg aead_algos[] = { > .setkey = artpec6_crypto_aead_set_key, > .encrypt = artpec6_crypto_aead_encrypt, > .decrypt = artpec6_crypto_aead_decrypt, > - .ivsize = AES_BLOCK_SIZE, > + .ivsize = 12, GCM_AES_IV_SIZE ? Regards
diff --git a/drivers/crypto/axis/artpec6_crypto.c b/drivers/crypto/axis/artpec6_crypto.c index 456278440863..4de1996120e7 100644 --- a/drivers/crypto/axis/artpec6_crypto.c +++ b/drivers/crypto/axis/artpec6_crypto.c @@ -1934,7 +1934,7 @@ static int artpec6_crypto_prepare_aead(struct aead_request *areq) memcpy(req_ctx->hw_ctx.J0, areq->iv, crypto_aead_ivsize(cipher)); // The HW omits the initial increment of the counter field. - crypto_inc(req_ctx->hw_ctx.J0+12, 4); + memcpy(req_ctx->hw_ctx.J0+12, "\x00\x00\x00\x01", 4); ret = artpec6_crypto_setup_out_descr(common, &req_ctx->hw_ctx, sizeof(struct artpec6_crypto_aead_hw_ctx), false, false); @@ -2956,7 +2956,7 @@ static struct aead_alg aead_algos[] = { .setkey = artpec6_crypto_aead_set_key, .encrypt = artpec6_crypto_aead_encrypt, .decrypt = artpec6_crypto_aead_decrypt, - .ivsize = AES_BLOCK_SIZE, + .ivsize = 12, .maxauthsize = AES_BLOCK_SIZE, .base = {
The IV size should not include the 32 bit counter. Because we had the IV size set as 16 the transform only worked when the IV input was zero padded. Fixes: a21eb94fc4d3 ("crypto: axis - add ARTPEC-6/7 crypto accelerator driver") Signed-off-by: Lars Persson <larper@axis.com> --- drivers/crypto/axis/artpec6_crypto.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)