@@ -82,10 +82,10 @@ static struct resource mmcsd0_resources[] = {
},
/* DMA channels: RX, then TX */
{
- .start = DAVINCI_DMA_MMCRXEVT,
+ .start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCRXEVT),
.flags = IORESOURCE_DMA,
}, {
- .start = DAVINCI_DMA_MMCTXEVT,
+ .start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCTXEVT),
.flags = IORESOURCE_DMA,
},
};
@@ -119,10 +119,10 @@ static struct resource mmcsd1_resources[] = {
},
/* DMA channels: RX, then TX */
{
- .start = 30, /* rx */
+ .start = EDMA_CTLR_CHAN(0, 30), /* rx */
.flags = IORESOURCE_DMA,
}, {
- .start = 31, /* tx */
+ .start = EDMA_CTLR_CHAN(0, 31), /* tx */
.flags = IORESOURCE_DMA,
},
};
@@ -114,95 +114,105 @@
static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
-static inline unsigned int edma_read(int offset)
+static inline unsigned int edma_read(unsigned ctlr, int offset)
{
- return (unsigned int)__raw_readl(edmacc_regs_base + offset);
+ return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
}
-static inline void edma_write(int offset, int val)
+static inline void edma_write(unsigned ctlr, int offset, int val)
{
- __raw_writel(val, edmacc_regs_base + offset);
+ __raw_writel(val, edmacc_regs_base[ctlr] + offset);
}
-static inline void edma_modify(int offset, unsigned and, unsigned or)
+static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
+ unsigned or)
{
- unsigned val = edma_read(offset);
+ unsigned val = edma_read(ctlr, offset);
val &= and;
val |= or;
- edma_write(offset, val);
+ edma_write(ctlr, offset, val);
}
-static inline void edma_and(int offset, unsigned and)
+static inline void edma_and(unsigned ctlr, int offset, unsigned and)
{
- unsigned val = edma_read(offset);
+ unsigned val = edma_read(ctlr, offset);
val &= and;
- edma_write(offset, val);
+ edma_write(ctlr, offset, val);
}
-static inline void edma_or(int offset, unsigned or)
+static inline void edma_or(unsigned ctlr, int offset, unsigned or)
{
- unsigned val = edma_read(offset);
+ unsigned val = edma_read(ctlr, offset);
val |= or;
- edma_write(offset, val);
+ edma_write(ctlr, offset, val);
}
-static inline unsigned int edma_read_array(int offset, int i)
+static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
{
- return edma_read(offset + (i << 2));
+ return edma_read(ctlr, offset + (i << 2));
}
-static inline void edma_write_array(int offset, int i, unsigned val)
+static inline void edma_write_array(unsigned ctlr, int offset, int i,
+ unsigned val)
{
- edma_write(offset + (i << 2), val);
+ edma_write(ctlr, offset + (i << 2), val);
}
-static inline void edma_modify_array(int offset, int i,
+static inline void edma_modify_array(unsigned ctlr, int offset, int i,
unsigned and, unsigned or)
{
- edma_modify(offset + (i << 2), and, or);
+ edma_modify(ctlr, offset + (i << 2), and, or);
}
-static inline void edma_or_array(int offset, int i, unsigned or)
+static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
{
- edma_or(offset + (i << 2), or);
+ edma_or(ctlr, offset + (i << 2), or);
}
-static inline void edma_or_array2(int offset, int i, int j, unsigned or)
+static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
+ unsigned or)
{
- edma_or(offset + ((i*2 + j) << 2), or);
+ edma_or(ctlr, offset + ((i*2 + j) << 2), or);
}
-static inline void edma_write_array2(int offset, int i, int j, unsigned val)
+static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
+ unsigned val)
{
- edma_write(offset + ((i*2 + j) << 2), val);
+ edma_write(ctlr, offset + ((i*2 + j) << 2), val);
}
-static inline unsigned int edma_shadow0_read(int offset)
+static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
{
- return edma_read(EDMA_SHADOW0 + offset);
+ return edma_read(ctlr, EDMA_SHADOW0 + offset);
}
-static inline unsigned int edma_shadow0_read_array(int offset, int i)
+static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
+ int i)
{
- return edma_read(EDMA_SHADOW0 + offset + (i << 2));
+ return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
}
-static inline void edma_shadow0_write(int offset, unsigned val)
+static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
{
- edma_write(EDMA_SHADOW0 + offset, val);
+ edma_write(ctlr, EDMA_SHADOW0 + offset, val);
}
-static inline void edma_shadow0_write_array(int offset, int i, unsigned val)
+static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
+ unsigned val)
{
- edma_write(EDMA_SHADOW0 + offset + (i << 2), val);
+ edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
}
-static inline unsigned int edma_parm_read(int offset, int param_no)
+static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
+ int param_no)
{
- return edma_read(EDMA_PARM + offset + (param_no << 5));
+ return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
}
-static inline void edma_parm_write(int offset, int param_no, unsigned val)
+static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
+ unsigned val)
{
- edma_write(EDMA_PARM + offset + (param_no << 5), val);
+ edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
}
-static inline void edma_parm_modify(int offset, int param_no,
+static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
unsigned and, unsigned or)
{
- edma_modify(EDMA_PARM + offset + (param_no << 5), and, or);
+ edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
}
-static inline void edma_parm_and(int offset, int param_no, unsigned and)
+static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
+ unsigned and)
{
- edma_and(EDMA_PARM + offset + (param_no << 5), and);
+ edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
}
-static inline void edma_parm_or(int offset, int param_no, unsigned or)
+static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
+ unsigned or)
{
- edma_or(EDMA_PARM + offset + (param_no << 5), or);
+ edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
}
/*****************************************************************************/
@@ -266,7 +276,8 @@ queue_priority_mapping[EDMA_MAX_EVQUE + 1][2] = {
/*****************************************************************************/
-static void map_dmach_queue(unsigned ch_no, enum dma_event_q queue_no)
+static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
+ enum dma_event_q queue_no)
{
int bit = (ch_no & 0x7) * 4;
@@ -275,20 +286,22 @@ static void map_dmach_queue(unsigned ch_no, enum dma_event_q queue_no)
queue_no = EVENTQ_1;
queue_no &= 7;
- edma_modify_array(EDMA_DMAQNUM, (ch_no >> 3),
+ edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
~(0x7 << bit), queue_no << bit);
}
-static void __init map_queue_tc(int queue_no, int tc_no)
+static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no)
{
int bit = queue_no * 4;
- edma_modify(EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
+ edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
}
-static void __init assign_priority_to_queue(int queue_no, int priority)
+static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
+ int priority)
{
int bit = queue_no * 4;
- edma_modify(EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
+ edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
+ ((priority & 0x7) << bit));
}
static inline void
@@ -296,22 +309,39 @@ setup_dma_interrupt(unsigned lch,
void (*callback)(unsigned channel, u16 ch_status, void *data),
void *data)
{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(lch);
+ lch = EDMA_CHAN_SLOT(lch);
+
if (!callback) {
- edma_shadow0_write_array(SH_IECR, lch >> 5,
+ edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
(1 << (lch & 0x1f)));
}
- intr_data[lch].callback = callback;
- intr_data[lch].data = data;
+ edma_info[ctlr]->intr_data[lch].callback = callback;
+ edma_info[ctlr]->intr_data[lch].data = data;
if (callback) {
- edma_shadow0_write_array(SH_ICR, lch >> 5,
+ edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
(1 << (lch & 0x1f)));
- edma_shadow0_write_array(SH_IESR, lch >> 5,
+ edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
(1 << (lch & 0x1f)));
}
}
+static int irq2ctlr(int irq)
+{
+ if (irq >= edma_info[0]->irq_res_start &&
+ irq <= edma_info[0]->irq_res_end)
+ return 0;
+ else if (irq >= edma_info[1]->irq_res_start &&
+ irq <= edma_info[1]->irq_res_end)
+ return 1;
+
+ return -1;
+}
+
/******************************************************************************
*
* DMA interrupt handler
@@ -320,32 +350,39 @@ setup_dma_interrupt(unsigned lch,
static irqreturn_t dma_irq_handler(int irq, void *data)
{
int i;
+ unsigned ctlr;
unsigned int cnt = 0;
+ ctlr = irq2ctlr(irq);
+
dev_dbg(data, "dma_irq_handler\n");
- if ((edma_shadow0_read_array(SH_IPR, 0) == 0)
- && (edma_shadow0_read_array(SH_IPR, 1) == 0))
+ if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0)
+ && (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
return IRQ_NONE;
while (1) {
int j;
- if (edma_shadow0_read_array(SH_IPR, 0))
+ if (edma_shadow0_read_array(ctlr, SH_IPR, 0))
j = 0;
- else if (edma_shadow0_read_array(SH_IPR, 1))
+ else if (edma_shadow0_read_array(ctlr, SH_IPR, 1))
j = 1;
else
break;
dev_dbg(data, "IPR%d %08x\n", j,
- edma_shadow0_read_array(SH_IPR, j));
+ edma_shadow0_read_array(ctlr, SH_IPR, j));
for (i = 0; i < 32; i++) {
int k = (j << 5) + i;
- if (edma_shadow0_read_array(SH_IPR, j) & (1 << i)) {
+ if (edma_shadow0_read_array(ctlr, SH_IPR, j) &
+ (1 << i)) {
/* Clear the corresponding IPR bits */
- edma_shadow0_write_array(SH_ICR, j, (1 << i));
- if (intr_data[k].callback) {
- intr_data[k].callback(k, DMA_COMPLETE,
- intr_data[k].data);
+ edma_shadow0_write_array(ctlr, SH_ICR, j,
+ (1 << i));
+ if (edma_info[ctlr]->intr_data[k].callback) {
+ edma_info[ctlr]->intr_data[k].callback(
+ k, DMA_COMPLETE,
+ edma_info[ctlr]->intr_data[k].
+ data);
}
}
}
@@ -353,7 +390,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
if (cnt > 10)
break;
}
- edma_shadow0_write(SH_IEVAL, 1);
+ edma_shadow0_write(ctlr, SH_IEVAL, 1);
return IRQ_HANDLED;
}
@@ -365,78 +402,87 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
static irqreturn_t dma_ccerr_handler(int irq, void *data)
{
int i;
+ unsigned ctlr;
unsigned int cnt = 0;
+ ctlr = irq2ctlr(irq);
+
dev_dbg(data, "dma_ccerr_handler\n");
- if ((edma_read_array(EDMA_EMR, 0) == 0) &&
- (edma_read_array(EDMA_EMR, 1) == 0) &&
- (edma_read(EDMA_QEMR) == 0) && (edma_read(EDMA_CCERR) == 0))
+ if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
+ (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
+ (edma_read(ctlr, EDMA_QEMR) == 0) &&
+ (edma_read(ctlr, EDMA_CCERR) == 0))
return IRQ_NONE;
while (1) {
int j = -1;
- if (edma_read_array(EDMA_EMR, 0))
+ if (edma_read_array(ctlr, EDMA_EMR, 0))
j = 0;
- else if (edma_read_array(EDMA_EMR, 1))
+ else if (edma_read_array(ctlr, EDMA_EMR, 1))
j = 1;
if (j >= 0) {
dev_dbg(data, "EMR%d %08x\n", j,
- edma_read_array(EDMA_EMR, j));
+ edma_read_array(ctlr, EDMA_EMR, j));
for (i = 0; i < 32; i++) {
int k = (j << 5) + i;
- if (edma_read_array(EDMA_EMR, j) & (1 << i)) {
+ if (edma_read_array(ctlr, EDMA_EMR, j) &
+ (1 << i)) {
/* Clear the corresponding EMR bits */
- edma_write_array(EDMA_EMCR, j, 1 << i);
+ edma_write_array(ctlr, EDMA_EMCR, j,
+ 1 << i);
/* Clear any SER */
- edma_shadow0_write_array(SH_SECR, j,
- (1 << i));
- if (intr_data[k].callback) {
- intr_data[k].callback(k,
- DMA_CC_ERROR,
- intr_data
- [k].data);
+ edma_shadow0_write_array(ctlr, SH_SECR,
+ j, (1 << i));
+ if (edma_info[ctlr]->intr_data[k].
+ callback) {
+ edma_info[ctlr]->intr_data[k].
+ callback(k,
+ DMA_CC_ERROR,
+ edma_info[ctlr]->intr_data
+ [k].data);
}
}
}
- } else if (edma_read(EDMA_QEMR)) {
+ } else if (edma_read(ctlr, EDMA_QEMR)) {
dev_dbg(data, "QEMR %02x\n",
- edma_read(EDMA_QEMR));
+ edma_read(ctlr, EDMA_QEMR));
for (i = 0; i < 8; i++) {
- if (edma_read(EDMA_QEMR) & (1 << i)) {
+ if (edma_read(ctlr, EDMA_QEMR) & (1 << i)) {
/* Clear the corresponding IPR bits */
- edma_write(EDMA_QEMCR, 1 << i);
- edma_shadow0_write(SH_QSECR, (1 << i));
+ edma_write(ctlr, EDMA_QEMCR, 1 << i);
+ edma_shadow0_write(ctlr, SH_QSECR,
+ (1 << i));
/* NOTE: not reported!! */
}
}
- } else if (edma_read(EDMA_CCERR)) {
+ } else if (edma_read(ctlr, EDMA_CCERR)) {
dev_dbg(data, "CCERR %08x\n",
- edma_read(EDMA_CCERR));
+ edma_read(ctlr, EDMA_CCERR));
/* FIXME: CCERR.BIT(16) ignored! much better
* to just write CCERRCLR with CCERR value...
*/
for (i = 0; i < 8; i++) {
- if (edma_read(EDMA_CCERR) & (1 << i)) {
+ if (edma_read(ctlr, EDMA_CCERR) & (1 << i)) {
/* Clear the corresponding IPR bits */
- edma_write(EDMA_CCERRCLR, 1 << i);
+ edma_write(ctlr, EDMA_CCERRCLR, 1 << i);
/* NOTE: not reported!! */
}
}
}
- if ((edma_read_array(EDMA_EMR, 0) == 0)
- && (edma_read_array(EDMA_EMR, 1) == 0)
- && (edma_read(EDMA_QEMR) == 0)
- && (edma_read(EDMA_CCERR) == 0)) {
+ if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0)
+ && (edma_read_array(ctlr, EDMA_EMR, 1) == 0)
+ && (edma_read(ctlr, EDMA_QEMR) == 0)
+ && (edma_read(ctlr, EDMA_CCERR) == 0)) {
break;
}
cnt++;
if (cnt > 10)
break;
}
- edma_write(EDMA_EEVAL, 1);
+ edma_write(ctlr, EDMA_EEVAL, 1);
return IRQ_HANDLED;
}
@@ -499,35 +545,53 @@ int edma_alloc_channel(int channel,
void *data,
enum dma_event_q eventq_no)
{
+ unsigned i, done, ctlr = 0;
+
+ if (channel >= 0) {
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+ }
+
if (channel < 0) {
- channel = 0;
- for (;;) {
- channel = find_next_bit(edma_noevent,
- num_channels, channel);
- if (channel == num_channels)
- return -ENOMEM;
- if (!test_and_set_bit(channel, edma_inuse))
+ for (i = 0; i < EDMA_MAX_CC; i++) {
+ channel = 0;
+ for (;;) {
+ channel = find_next_bit(edma_info[i]->
+ edma_noevent,
+ edma_info[i]->num_channels,
+ channel);
+ if (channel == edma_info[i]->num_channels)
+ return -ENOMEM;
+ if (!test_and_set_bit(channel,
+ edma_info[i]->edma_inuse)) {
+ done = 1;
+ ctlr = i;
+ break;
+ }
+ channel++;
+ }
+ if (done)
break;
- channel++;
}
- } else if (channel >= num_channels) {
+ } else if (channel >= edma_info[ctlr]->num_channels) {
return -EINVAL;
- } else if (test_and_set_bit(channel, edma_inuse)) {
+ } else if (test_and_set_bit(channel, edma_info[ctlr]->edma_inuse)) {
return -EBUSY;
}
/* ensure access through shadow region 0 */
- edma_or_array2(EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f));
+ edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f));
/* ensure no events are pending */
- edma_stop(channel);
- memcpy_toio(edmacc_regs_base + PARM_OFFSET(channel),
+ edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
+ memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
&dummy_paramset, PARM_SIZE);
if (callback)
- setup_dma_interrupt(channel, callback, data);
+ setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
+ callback, data);
- map_dmach_queue(channel, eventq_no);
+ map_dmach_queue(ctlr, channel, eventq_no);
return channel;
}
@@ -547,15 +611,20 @@ EXPORT_SYMBOL(edma_alloc_channel);
*/
void edma_free_channel(unsigned channel)
{
- if (channel >= num_channels)
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel >= edma_info[ctlr]->num_channels)
return;
setup_dma_interrupt(channel, NULL, NULL);
/* REVISIT should probably take out of shadow region 0 */
- memcpy_toio(edmacc_regs_base + PARM_OFFSET(channel),
+ memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
&dummy_paramset, PARM_SIZE);
- clear_bit(channel, edma_inuse);
+ clear_bit(channel, edma_info[ctlr]->edma_inuse);
}
EXPORT_SYMBOL(edma_free_channel);
@@ -573,28 +642,33 @@ EXPORT_SYMBOL(edma_free_channel);
*
* Returns the number of the slot, else negative errno.
*/
-int edma_alloc_slot(int slot)
+int edma_alloc_slot(unsigned ctlr, int slot)
{
+ if (slot >= 0)
+ slot = EDMA_CHAN_SLOT(slot);
+
if (slot < 0) {
- slot = num_channels;
+ slot = edma_info[ctlr]->num_channels;
for (;;) {
- slot = find_next_zero_bit(edma_inuse,
- num_slots, slot);
- if (slot == num_slots)
+ slot = find_next_zero_bit(edma_info[ctlr]->edma_inuse,
+ edma_info[ctlr]->num_slots, slot);
+ if (slot == edma_info[ctlr]->num_slots)
return -ENOMEM;
- if (!test_and_set_bit(slot, edma_inuse))
+ if (!test_and_set_bit(slot,
+ edma_info[ctlr]->edma_inuse))
break;
}
- } else if (slot < num_channels || slot >= num_slots) {
+ } else if (slot < edma_info[ctlr]->num_channels ||
+ slot >= edma_info[ctlr]->num_slots) {
return -EINVAL;
- } else if (test_and_set_bit(slot, edma_inuse)) {
+ } else if (test_and_set_bit(slot, edma_info[ctlr]->edma_inuse)) {
return -EBUSY;
}
- memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot),
+ memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
&dummy_paramset, PARM_SIZE);
- return slot;
+ return EDMA_CTLR_CHAN(ctlr, slot);
}
EXPORT_SYMBOL(edma_alloc_slot);
@@ -608,12 +682,18 @@ EXPORT_SYMBOL(edma_alloc_slot);
*/
void edma_free_slot(unsigned slot)
{
- if (slot < num_channels || slot >= num_slots)
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot < edma_info[ctlr]->num_channels ||
+ slot >= edma_info[ctlr]->num_slots)
return;
- memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot),
+ memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
&dummy_paramset, PARM_SIZE);
- clear_bit(slot, edma_inuse);
+ clear_bit(slot, edma_info[ctlr]->edma_inuse);
}
EXPORT_SYMBOL(edma_free_slot);
@@ -635,8 +715,13 @@ EXPORT_SYMBOL(edma_free_slot);
void edma_set_src(unsigned slot, dma_addr_t src_port,
enum address_mode mode, enum fifo_width width)
{
- if (slot < num_slots) {
- unsigned int i = edma_parm_read(PARM_OPT, slot);
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot < edma_info[ctlr]->num_slots) {
+ unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
if (mode) {
/* set SAM and program FWID */
@@ -645,11 +730,11 @@ void edma_set_src(unsigned slot, dma_addr_t src_port,
/* clear SAM */
i &= ~SAM;
}
- edma_parm_write(PARM_OPT, slot, i);
+ edma_parm_write(ctlr, PARM_OPT, slot, i);
/* set the source port address
in source register of param structure */
- edma_parm_write(PARM_SRC, slot, src_port);
+ edma_parm_write(ctlr, PARM_SRC, slot, src_port);
}
}
EXPORT_SYMBOL(edma_set_src);
@@ -668,8 +753,13 @@ EXPORT_SYMBOL(edma_set_src);
void edma_set_dest(unsigned slot, dma_addr_t dest_port,
enum address_mode mode, enum fifo_width width)
{
- if (slot < num_slots) {
- unsigned int i = edma_parm_read(PARM_OPT, slot);
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot < edma_info[ctlr]->num_slots) {
+ unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
if (mode) {
/* set DAM and program FWID */
@@ -678,10 +768,10 @@ void edma_set_dest(unsigned slot, dma_addr_t dest_port,
/* clear DAM */
i &= ~DAM;
}
- edma_parm_write(PARM_OPT, slot, i);
+ edma_parm_write(ctlr, PARM_OPT, slot, i);
/* set the destination port address
in dest register of param structure */
- edma_parm_write(PARM_DST, slot, dest_port);
+ edma_parm_write(ctlr, PARM_DST, slot, dest_port);
}
}
EXPORT_SYMBOL(edma_set_dest);
@@ -698,8 +788,12 @@ EXPORT_SYMBOL(edma_set_dest);
void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst)
{
struct edmacc_param temp;
+ unsigned ctlr;
- edma_read_slot(slot, &temp);
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp);
if (src != NULL)
*src = temp.src;
if (dst != NULL)
@@ -719,10 +813,15 @@ EXPORT_SYMBOL(edma_get_position);
*/
void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
{
- if (slot < num_slots) {
- edma_parm_modify(PARM_SRC_DST_BIDX, slot,
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot < edma_info[ctlr]->num_slots) {
+ edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
0xffff0000, src_bidx);
- edma_parm_modify(PARM_SRC_DST_CIDX, slot,
+ edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
0xffff0000, src_cidx);
}
}
@@ -740,10 +839,15 @@ EXPORT_SYMBOL(edma_set_src_index);
*/
void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
{
- if (slot < num_slots) {
- edma_parm_modify(PARM_SRC_DST_BIDX, slot,
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot < edma_info[ctlr]->num_slots) {
+ edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
0x0000ffff, dest_bidx << 16);
- edma_parm_modify(PARM_SRC_DST_CIDX, slot,
+ edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
0x0000ffff, dest_cidx << 16);
}
}
@@ -782,16 +886,21 @@ void edma_set_transfer_params(unsigned slot,
u16 acnt, u16 bcnt, u16 ccnt,
u16 bcnt_rld, enum sync_dimension sync_mode)
{
- if (slot < num_slots) {
- edma_parm_modify(PARM_LINK_BCNTRLD, slot,
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot < edma_info[ctlr]->num_slots) {
+ edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
0x0000ffff, bcnt_rld << 16);
if (sync_mode == ASYNC)
- edma_parm_and(PARM_OPT, slot, ~SYNCDIM);
+ edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
else
- edma_parm_or(PARM_OPT, slot, SYNCDIM);
+ edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
/* Set the acount, bcount, ccount registers */
- edma_parm_write(PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
- edma_parm_write(PARM_CCNT, slot, ccnt);
+ edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
+ edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
}
}
EXPORT_SYMBOL(edma_set_transfer_params);
@@ -805,11 +914,19 @@ EXPORT_SYMBOL(edma_set_transfer_params);
*/
void edma_link(unsigned from, unsigned to)
{
- if (from >= num_slots)
+ unsigned ctlr_from, ctlr_to;
+
+ ctlr_from = EDMA_CTLR(from);
+ from = EDMA_CHAN_SLOT(from);
+ ctlr_to = EDMA_CTLR(to);
+ to = EDMA_CHAN_SLOT(to);
+
+ if (from >= edma_info[ctlr_from]->num_slots)
return;
- if (to >= num_slots)
+ if (to >= edma_info[ctlr_to]->num_slots)
return;
- edma_parm_modify(PARM_LINK_BCNTRLD, from, 0xffff0000, PARM_OFFSET(to));
+ edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
+ PARM_OFFSET(to));
}
EXPORT_SYMBOL(edma_link);
@@ -822,9 +939,14 @@ EXPORT_SYMBOL(edma_link);
*/
void edma_unlink(unsigned from)
{
- if (from >= num_slots)
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(from);
+ from = EDMA_CHAN_SLOT(from);
+
+ if (from >= edma_info[ctlr]->num_slots)
return;
- edma_parm_or(PARM_LINK_BCNTRLD, from, 0xffff);
+ edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
}
EXPORT_SYMBOL(edma_unlink);
@@ -844,9 +966,15 @@ EXPORT_SYMBOL(edma_unlink);
*/
void edma_write_slot(unsigned slot, const struct edmacc_param *param)
{
- if (slot >= num_slots)
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot >= edma_info[ctlr]->num_slots)
return;
- memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot), param, PARM_SIZE);
+ memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
+ PARM_SIZE);
}
EXPORT_SYMBOL(edma_write_slot);
@@ -860,9 +988,15 @@ EXPORT_SYMBOL(edma_write_slot);
*/
void edma_read_slot(unsigned slot, struct edmacc_param *param)
{
- if (slot >= num_slots)
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot >= edma_info[ctlr]->num_slots)
return;
- memcpy_fromio(param, edmacc_regs_base + PARM_OFFSET(slot), PARM_SIZE);
+ memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
+ PARM_SIZE);
}
EXPORT_SYMBOL(edma_read_slot);
@@ -879,10 +1013,15 @@ EXPORT_SYMBOL(edma_read_slot);
*/
void edma_pause(unsigned channel)
{
- if (channel < num_channels) {
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel < edma_info[ctlr]->num_channels) {
unsigned int mask = (1 << (channel & 0x1f));
- edma_shadow0_write_array(SH_EECR, channel >> 5, mask);
+ edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
}
}
EXPORT_SYMBOL(edma_pause);
@@ -895,10 +1034,15 @@ EXPORT_SYMBOL(edma_pause);
*/
void edma_resume(unsigned channel)
{
- if (channel < num_channels) {
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel < edma_info[ctlr]->num_channels) {
unsigned int mask = (1 << (channel & 0x1f));
- edma_shadow0_write_array(SH_EESR, channel >> 5, mask);
+ edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
}
}
EXPORT_SYMBOL(edma_resume);
@@ -916,28 +1060,33 @@ EXPORT_SYMBOL(edma_resume);
*/
int edma_start(unsigned channel)
{
- if (channel < num_channels) {
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel < edma_info[ctlr]->num_channels) {
int j = channel >> 5;
unsigned int mask = (1 << (channel & 0x1f));
/* EDMA channels without event association */
- if (test_bit(channel, edma_noevent)) {
+ if (test_bit(channel, edma_info[ctlr]->edma_noevent)) {
pr_debug("EDMA: ESR%d %08x\n", j,
- edma_shadow0_read_array(SH_ESR, j));
- edma_shadow0_write_array(SH_ESR, j, mask);
+ edma_shadow0_read_array(ctlr, SH_ESR, j));
+ edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
return 0;
}
/* EDMA channel with event association */
pr_debug("EDMA: ER%d %08x\n", j,
- edma_shadow0_read_array(SH_ER, j));
+ edma_shadow0_read_array(ctlr, SH_ER, j));
/* Clear any pending error */
- edma_write_array(EDMA_EMCR, j, mask);
+ edma_write_array(ctlr, EDMA_EMCR, j, mask);
/* Clear any SER */
- edma_shadow0_write_array(SH_SECR, j, mask);
- edma_shadow0_write_array(SH_EESR, j, mask);
+ edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
+ edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
pr_debug("EDMA: EER%d %08x\n", j,
- edma_shadow0_read_array(SH_EER, j));
+ edma_shadow0_read_array(ctlr, SH_EER, j));
return 0;
}
@@ -956,17 +1105,22 @@ EXPORT_SYMBOL(edma_start);
*/
void edma_stop(unsigned channel)
{
- if (channel < num_channels) {
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel < edma_info[ctlr]->num_channels) {
int j = channel >> 5;
unsigned int mask = (1 << (channel & 0x1f));
- edma_shadow0_write_array(SH_EECR, j, mask);
- edma_shadow0_write_array(SH_ECR, j, mask);
- edma_shadow0_write_array(SH_SECR, j, mask);
- edma_write_array(EDMA_EMCR, j, mask);
+ edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
+ edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
+ edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
+ edma_write_array(ctlr, EDMA_EMCR, j, mask);
pr_debug("EDMA: EER%d %08x\n", j,
- edma_shadow0_read_array(SH_EER, j));
+ edma_shadow0_read_array(ctlr, SH_EER, j));
/* REVISIT: consider guarding against inappropriate event
* chaining by overwriting with dummy_paramset.
@@ -990,18 +1144,23 @@ EXPORT_SYMBOL(edma_stop);
void edma_clean_channel(unsigned channel)
{
- if (channel < num_channels) {
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel < edma_info[ctlr]->num_channels) {
int j = (channel >> 5);
unsigned int mask = 1 << (channel & 0x1f);
pr_debug("EDMA: EMR%d %08x\n", j,
- edma_read_array(EDMA_EMR, j));
- edma_shadow0_write_array(SH_ECR, j, mask);
+ edma_read_array(ctlr, EDMA_EMR, j));
+ edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
/* Clear the corresponding EMR bits */
- edma_write_array(EDMA_EMCR, j, mask);
+ edma_write_array(ctlr, EDMA_EMCR, j, mask);
/* Clear any SER */
- edma_shadow0_write_array(SH_SECR, j, mask);
- edma_write(EDMA_CCERRCLR, (1 << 16) | 0x3);
+ edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
+ edma_write(ctlr, EDMA_CCERRCLR, (1 << 16) | 0x3);
}
}
EXPORT_SYMBOL(edma_clean_channel);
@@ -1013,12 +1172,17 @@ EXPORT_SYMBOL(edma_clean_channel);
*/
void edma_clear_event(unsigned channel)
{
- if (channel >= num_channels)
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel >= edma_info[ctlr]->num_channels)
return;
if (channel < 32)
- edma_write(EDMA_ECR, 1 << channel);
+ edma_write(ctlr, EDMA_ECR, 1 << channel);
else
- edma_write(EDMA_ECRH, 1 << (channel - 32));
+ edma_write(ctlr, EDMA_ECRH, 1 << (channel - 32));
}
EXPORT_SYMBOL(edma_clear_event);
@@ -170,6 +170,10 @@ enum sync_dimension {
ABSYNC = 1
};
+#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
+#define EDMA_CTLR(i) ((i) >> 16)
+#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
+
#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
@@ -180,7 +184,7 @@ int edma_alloc_channel(int channel,
void edma_free_channel(unsigned channel);
/* alloc/free parameter RAM slots */
-int edma_alloc_slot(int slot);
+int edma_alloc_slot(unsigned ctlr, int slot);
void edma_free_slot(unsigned slot);
/* calls that operate on part of a parameter RAM slot */