From patchwork Fri Jul 10 10:58:00 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rajashekhara, Sudhakar" X-Patchwork-Id: 34966 Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n6ABmD8d005980 for ; Fri, 10 Jul 2009 11:48:13 GMT Received: from dlep33.itg.ti.com ([157.170.170.112]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id n6ABjxBJ023668; Fri, 10 Jul 2009 06:46:04 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id n6ABjx4D019615; Fri, 10 Jul 2009 06:45:59 -0500 (CDT) Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 53DE980627; Fri, 10 Jul 2009 06:45:58 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dflp53.itg.ti.com (dflp53.itg.ti.com [128.247.5.6]) by linux.omap.com (Postfix) with ESMTP id A1D1E80626 for ; Fri, 10 Jul 2009 06:45:55 -0500 (CDT) Received: from tidmzi-ftp.india.ext.ti.com (localhost [127.0.0.1]) by dflp53.itg.ti.com (8.13.8/8.13.8) with SMTP id n6ABjqbE029135 for ; Fri, 10 Jul 2009 06:45:53 -0500 (CDT) Received: from symphonyindia.ti.com (symphony-ftp [192.168.247.11]) by tidmzi-ftp.india.ext.ti.com (Postfix) with SMTP id 1E9953888E for ; Fri, 10 Jul 2009 17:13:07 +0530 (IST) Received: from localhost.localdomain ([192.168.247.76]) by symphonyindia.ti.com (8.12.10/8.12.10) with ESMTP id n6ABfZEZ028655; Fri, 10 Jul 2009 17:11:35 +0530 From: Sudhakar Rajashekhara To: davinci-linux-open-source@linux.davincidsp.com Date: Fri, 10 Jul 2009 06:58:00 -0400 Message-Id: <1247223480-8478-1-git-send-email-sudhakar.raj@ti.com> X-Mailer: git-send-email 1.5.6 Cc: Subject: [PATCH v2 1/2] davinci: Add base DA850/OMAP-L138 SoC support X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.4 Precedence: list List-Id: davinci-linux-open-source.linux.davincidsp.com List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: davinci-linux-open-source-bounces@linux.davincidsp.com Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com The DA850/OMAP-L138 is a new SoC from TI in the same family as DA830/OMAP-L137. Major changes include better support for power management, support for SATA devices and McBSP (same IP as DM644x). DA850/OMAP-L138 documents are available at http://focus.ti.com/docs/prod/folders/print/omap-l138.html. Signed-off-by: Sudhakar Rajashekhara --- This patch set depends on the following patch which I have submitted earlier: [PATCH] davinci: Move the da830/omap-l137 #defines to header file arch/arm/mach-davinci/Kconfig | 5 + arch/arm/mach-davinci/Makefile | 1 + arch/arm/mach-davinci/da850.c | 623 ++++++++++++++++++++++++++ arch/arm/mach-davinci/include/mach/cputype.h | 8 + arch/arm/mach-davinci/include/mach/da8xx.h | 8 + arch/arm/mach-davinci/include/mach/irqs.h | 63 +++- arch/arm/mach-davinci/include/mach/mux.h | 28 ++ arch/arm/mach-davinci/include/mach/psc.h | 4 + 8 files changed, 737 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-davinci/da850.c diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 646c569..1ee438e 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -33,6 +33,11 @@ config ARCH_DAVINCI_DA830 select CP_INTC select ARCH_DAVINCI_DA8XX +config ARCH_DAVINCI_DA850 + bool "DA850/OMAP-L138 based system" + select CP_INTC + select ARCH_DAVINCI_DA8XX + config ARCH_DAVINCI_DA8XX bool diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index d183b11..5f8a661 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o devices.o obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o devices.o obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o +obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o obj-$(CONFIG_AINTC) += irq.o obj-$(CONFIG_CP_INTC) += cp_intc.o diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c new file mode 100644 index 0000000..79d034a --- /dev/null +++ b/arch/arm/mach-davinci/da850.c @@ -0,0 +1,623 @@ +/* + * TI DA850/OMAP L138 chip specific setup + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * Derived from: arch/arm/mach-davinci/da830.c + * Original Copyrights follow: + * + * 2009 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clock.h" +#include "mux.h" + +#define DA850_PLL1_BASE 0x01e1a000 + +#define DA850_REF_FREQ 24000000 + +static struct pll_data pll0_data = { + .num = 1, + .phys_base = DA8XX_PLL0_BASE, + .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV, +}; + +static struct clk ref_clk = { + .name = "ref_clk", + .rate = DA850_REF_FREQ, +}; + +static struct clk pll0_clk = { + .name = "pll0", + .parent = &ref_clk, + .pll_data = &pll0_data, + .flags = CLK_PLL, +}; + +static struct clk pll0_aux_clk = { + .name = "pll0_aux_clk", + .parent = &pll0_clk, + .flags = CLK_PLL | PRE_PLL, +}; + +static struct clk pll0_sysclk2 = { + .name = "pll0_sysclk2", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV2, +}; + +static struct clk pll0_sysclk3 = { + .name = "pll0_sysclk3", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV3, +}; + +static struct clk pll0_sysclk4 = { + .name = "pll0_sysclk4", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV4, +}; + +static struct clk pll0_sysclk5 = { + .name = "pll0_sysclk5", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV5, +}; + +static struct clk pll0_sysclk6 = { + .name = "pll0_sysclk6", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV6, +}; + +static struct clk pll0_sysclk7 = { + .name = "pll0_sysclk7", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV7, +}; + +static struct pll_data pll1_data = { + .num = 2, + .phys_base = DA850_PLL1_BASE, + .flags = PLL_HAS_POSTDIV, +}; + +static struct clk pll1_clk = { + .name = "pll1", + .parent = &ref_clk, + .pll_data = &pll1_data, + .flags = CLK_PLL, +}; + +static struct clk pll1_aux_clk = { + .name = "pll1_aux_clk", + .parent = &pll1_clk, + .flags = CLK_PLL | PRE_PLL, +}; + +static struct clk pll1_sysclk2 = { + .name = "pll1_sysclk2", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV2, +}; + +static struct clk pll1_sysclk3 = { + .name = "pll1_sysclk3", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV3, +}; + +static struct clk pll1_sysclk4 = { + .name = "pll1_sysclk4", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV4, +}; + +static struct clk pll1_sysclk5 = { + .name = "pll1_sysclk5", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV5, +}; + +static struct clk pll1_sysclk6 = { + .name = "pll0_sysclk6", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV6, +}; + +static struct clk pll1_sysclk7 = { + .name = "pll1_sysclk7", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV7, +}; + +static struct clk i2c0_clk = { + .name = "i2c0", + .parent = &pll0_aux_clk, +}; + +static struct clk timerp64_0_clk = { + .name = "timer0", + .parent = &pll0_aux_clk, +}; + +static struct clk timerp64_1_clk = { + .name = "timer1", + .parent = &pll0_aux_clk, +}; + +static struct clk arm_rom_clk = { + .name = "arm_rom", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_ARM_RAM_ROM, + .flags = ALWAYS_ENABLED, +}; + +static struct clk tpcc0_clk = { + .name = "tpcc0", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_TPCC, + .flags = ALWAYS_ENABLED | CLK_PSC, +}; + +static struct clk tptc0_clk = { + .name = "tptc0", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_TPTC0, + .flags = ALWAYS_ENABLED, +}; + +static struct clk tptc1_clk = { + .name = "tptc1", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_TPTC1, + .flags = ALWAYS_ENABLED, +}; + +static struct clk tpcc1_clk = { + .name = "tpcc1", + .parent = &pll0_sysclk2, + .lpsc = DA850_LPSC1_TPCC1, + .flags = CLK_PSC | ALWAYS_ENABLED, + .psc_ctlr = 1, +}; + +static struct clk tptc2_clk = { + .name = "tptc2", + .parent = &pll0_sysclk2, + .lpsc = DA850_LPSC1_TPTC2, + .flags = ALWAYS_ENABLED, + .psc_ctlr = 1, +}; + +static struct clk uart0_clk = { + .name = "uart0", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_UART0, +}; + +static struct clk uart1_clk = { + .name = "uart1", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_UART1, + .psc_ctlr = 1, +}; + +static struct clk uart2_clk = { + .name = "uart2", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_UART2, + .psc_ctlr = 1, +}; + +static struct clk aintc_clk = { + .name = "aintc", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC0_AINTC, + .flags = ALWAYS_ENABLED, +}; + +static struct clk gpio_clk = { + .name = "gpio", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC1_GPIO, + .psc_ctlr = 1, +}; + +static struct clk i2c1_clk = { + .name = "i2c1", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC1_I2C, + .psc_ctlr = 1, +}; + +static struct clk emif3_clk = { + .name = "emif3", + .parent = &pll0_sysclk5, + .lpsc = DA8XX_LPSC1_EMIF3C, + .flags = ALWAYS_ENABLED, + .psc_ctlr = 1, +}; + +static struct clk arm_clk = { + .name = "arm", + .parent = &pll0_sysclk6, + .lpsc = DA8XX_LPSC0_ARM, + .flags = ALWAYS_ENABLED, +}; + +static struct clk rmii_clk = { + .name = "rmii", + .parent = &pll0_sysclk7, +}; + +static struct davinci_clk da850_clks[] = { + CLK(NULL, "ref", &ref_clk), + CLK(NULL, "pll0", &pll0_clk), + CLK(NULL, "pll0_aux", &pll0_aux_clk), + CLK(NULL, "pll0_sysclk2", &pll0_sysclk2), + CLK(NULL, "pll0_sysclk3", &pll0_sysclk3), + CLK(NULL, "pll0_sysclk4", &pll0_sysclk4), + CLK(NULL, "pll0_sysclk5", &pll0_sysclk5), + CLK(NULL, "pll0_sysclk6", &pll0_sysclk6), + CLK(NULL, "pll0_sysclk7", &pll0_sysclk7), + CLK(NULL, "pll1", &pll1_clk), + CLK(NULL, "pll1_aux", &pll1_aux_clk), + CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), + CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), + CLK(NULL, "pll1_sysclk4", &pll1_sysclk4), + CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), + CLK(NULL, "pll1_sysclk6", &pll1_sysclk6), + CLK(NULL, "pll1_sysclk7", &pll1_sysclk7), + CLK("i2c_davinci.1", NULL, &i2c0_clk), + CLK(NULL, "timer0", &timerp64_0_clk), + CLK("watchdog", NULL, &timerp64_1_clk), + CLK(NULL, "arm_rom", &arm_rom_clk), + CLK(NULL, "tpcc0", &tpcc0_clk), + CLK(NULL, "tptc0", &tptc0_clk), + CLK(NULL, "tptc1", &tptc1_clk), + CLK(NULL, "tpcc1", &tpcc1_clk), + CLK(NULL, "tptc2", &tptc2_clk), + CLK(NULL, "uart0", &uart0_clk), + CLK(NULL, "uart1", &uart1_clk), + CLK(NULL, "uart2", &uart2_clk), + CLK(NULL, "aintc", &aintc_clk), + CLK(NULL, "gpio", &gpio_clk), + CLK("i2c_davinci.2", NULL, &i2c1_clk), + CLK(NULL, "emif3", &emif3_clk), + CLK(NULL, "arm", &arm_clk), + CLK(NULL, "rmii", &rmii_clk), + CLK(NULL, NULL, NULL), +}; + +#define PINMUX0 0x00 +#define PINMUX1 0x04 +#define PINMUX2 0x08 +#define PINMUX3 0x0c +#define PINMUX4 0x10 +#define PINMUX5 0x14 +#define PINMUX6 0x18 +#define PINMUX7 0x1c +#define PINMUX8 0x20 +#define PINMUX9 0x24 +#define PINMUX10 0x28 +#define PINMUX11 0x2c +#define PINMUX12 0x30 +#define PINMUX13 0x34 +#define PINMUX14 0x38 +#define PINMUX15 0x3c +#define PINMUX16 0x40 +#define PINMUX17 0x44 +#define PINMUX18 0x48 +#define PINMUX19 0x4c + +/* + * Device specific mux setup + * + * soc description mux mode mode mux dbg + * reg offset mask mode + */ +static const struct mux_config da850_pins[] = { +#ifdef CONFIG_DAVINCI_MUX + /* UART0 function */ + MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false) + MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false) + MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false) + MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false) + /* UART1 function */ + MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false) + MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false) + /* UART2 function */ + MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false) + MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false) + /* I2C1 function */ + MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false) + MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false) + /* I2C0 function */ + MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false) + MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false) +#endif +}; + +const short da850_uart0_pins[] __initdata = { + DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD, + -1 +}; + +const short da850_uart1_pins[] __initdata = { + DA850_UART1_RXD, DA850_UART1_TXD, + -1 +}; + +const short da850_uart2_pins[] __initdata = { + DA850_UART2_RXD, DA850_UART2_TXD, + -1 +}; + +const short da850_i2c0_pins[] __initdata = { + DA850_I2C0_SDA, DA850_I2C0_SCL, + -1 +}; + +const short da850_i2c1_pins[] __initdata = { + DA850_I2C1_SCL, DA850_I2C1_SDA, + -1 +}; + +int da850_pinmux_setup(const short pins[]) +{ + int i, error = -EINVAL; + + if (pins) + for (i = 0; pins[i] >= 0; i++) { + error = davinci_cfg_reg(pins[i]); + if (error) + break; + } + + return error; +} + +/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ +static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = { + [IRQ_DA8XX_COMMTX] = 7, + [IRQ_DA8XX_COMMRX] = 7, + [IRQ_DA8XX_NINT] = 7, + [IRQ_DA8XX_EVTOUT0] = 7, + [IRQ_DA8XX_EVTOUT1] = 7, + [IRQ_DA8XX_EVTOUT2] = 7, + [IRQ_DA8XX_EVTOUT3] = 7, + [IRQ_DA8XX_EVTOUT4] = 7, + [IRQ_DA8XX_EVTOUT5] = 7, + [IRQ_DA8XX_EVTOUT6] = 7, + [IRQ_DA8XX_EVTOUT6] = 7, + [IRQ_DA8XX_EVTOUT7] = 7, + [IRQ_DA8XX_CCINT0] = 7, + [IRQ_DA8XX_CCERRINT] = 7, + [IRQ_DA8XX_TCERRINT0] = 7, + [IRQ_DA8XX_AEMIFINT] = 7, + [IRQ_DA8XX_I2CINT0] = 7, + [IRQ_DA8XX_MMCSDINT0] = 7, + [IRQ_DA8XX_MMCSDINT1] = 7, + [IRQ_DA8XX_ALLINT0] = 7, + [IRQ_DA8XX_RTC] = 7, + [IRQ_DA8XX_SPINT0] = 7, + [IRQ_DA8XX_TINT12_0] = 7, + [IRQ_DA8XX_TINT34_0] = 7, + [IRQ_DA8XX_TINT12_1] = 7, + [IRQ_DA8XX_TINT34_1] = 7, + [IRQ_DA8XX_UARTINT0] = 7, + [IRQ_DA8XX_KEYMGRINT] = 7, + [IRQ_DA8XX_SECINT] = 7, + [IRQ_DA8XX_SECKEYERR] = 7, + [IRQ_DA850_MPUADDRERR0] = 7, + [IRQ_DA850_MPUPROTERR0] = 7, + [IRQ_DA850_IOPUADDRERR0] = 7, + [IRQ_DA850_IOPUPROTERR0] = 7, + [IRQ_DA850_IOPUADDRERR1] = 7, + [IRQ_DA850_IOPUPROTERR1] = 7, + [IRQ_DA850_IOPUADDRERR2] = 7, + [IRQ_DA850_IOPUPROTERR2] = 7, + [IRQ_DA850_BOOTCFG_ADDR_ERR] = 7, + [IRQ_DA850_BOOTCFG_PROT_ERR] = 7, + [IRQ_DA850_MPUADDRERR1] = 7, + [IRQ_DA850_MPUPROTERR1] = 7, + [IRQ_DA850_IOPUADDRERR3] = 7, + [IRQ_DA850_IOPUPROTERR3] = 7, + [IRQ_DA850_IOPUADDRERR4] = 7, + [IRQ_DA850_IOPUPROTERR4] = 7, + [IRQ_DA850_IOPUADDRERR5] = 7, + [IRQ_DA850_IOPUPROTERR5] = 7, + [IRQ_DA850_MIOPU_BOOTCFG_ERR] = 7, + [IRQ_DA8XX_CHIPINT0] = 7, + [IRQ_DA8XX_CHIPINT1] = 7, + [IRQ_DA8XX_CHIPINT2] = 7, + [IRQ_DA8XX_CHIPINT3] = 7, + [IRQ_DA8XX_TCERRINT1] = 7, + [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7, + [IRQ_DA8XX_C0_RX_PULSE] = 7, + [IRQ_DA8XX_C0_TX_PULSE] = 7, + [IRQ_DA8XX_C0_MISC_PULSE] = 7, + [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7, + [IRQ_DA8XX_C1_RX_PULSE] = 7, + [IRQ_DA8XX_C1_TX_PULSE] = 7, + [IRQ_DA8XX_C1_MISC_PULSE] = 7, + [IRQ_DA8XX_MEMERR] = 7, + [IRQ_DA8XX_GPIO0] = 7, + [IRQ_DA8XX_GPIO1] = 7, + [IRQ_DA8XX_GPIO2] = 7, + [IRQ_DA8XX_GPIO3] = 7, + [IRQ_DA8XX_GPIO4] = 7, + [IRQ_DA8XX_GPIO5] = 7, + [IRQ_DA8XX_GPIO6] = 7, + [IRQ_DA8XX_GPIO7] = 7, + [IRQ_DA8XX_GPIO8] = 7, + [IRQ_DA8XX_I2CINT1] = 7, + [IRQ_DA8XX_LCDINT] = 7, + [IRQ_DA8XX_UARTINT1] = 7, + [IRQ_DA8XX_MCASPINT] = 7, + [IRQ_DA8XX_ALLINT1] = 7, + [IRQ_DA8XX_SPINT1] = 7, + [IRQ_DA8XX_UHPI_INT1] = 7, + [IRQ_DA8XX_USB_INT] = 7, + [IRQ_DA8XX_IRQN] = 7, + [IRQ_DA8XX_RWAKEUP] = 7, + [IRQ_DA8XX_UARTINT2] = 7, + [IRQ_DA8XX_DFTSSINT] = 7, + [IRQ_DA8XX_EHRPWM0] = 7, + [IRQ_DA8XX_EHRPWM0TZ] = 7, + [IRQ_DA8XX_EHRPWM1] = 7, + [IRQ_DA8XX_EHRPWM1TZ] = 7, + [IRQ_DA850_SATAINT] = 7, + [IRQ_DA850_TINT12_2] = 7, + [IRQ_DA850_TINT34_2] = 7, + [IRQ_DA850_TINTALL_2] = 7, + [IRQ_DA8XX_ECAP0] = 7, + [IRQ_DA8XX_ECAP1] = 7, + [IRQ_DA8XX_ECAP2] = 7, + [IRQ_DA850_MMCSDINT0_1] = 7, + [IRQ_DA850_MMCSDINT1_1] = 7, + [IRQ_DA850_T12CMPINT0_2] = 7, + [IRQ_DA850_T12CMPINT1_2] = 7, + [IRQ_DA850_T12CMPINT2_2] = 7, + [IRQ_DA850_T12CMPINT3_2] = 7, + [IRQ_DA850_T12CMPINT4_2] = 7, + [IRQ_DA850_T12CMPINT5_2] = 7, + [IRQ_DA850_T12CMPINT6_2] = 7, + [IRQ_DA850_T12CMPINT7_2] = 7, + [IRQ_DA850_T12CMPINT0_3] = 7, + [IRQ_DA850_T12CMPINT1_3] = 7, + [IRQ_DA850_T12CMPINT2_3] = 7, + [IRQ_DA850_T12CMPINT3_3] = 7, + [IRQ_DA850_T12CMPINT4_3] = 7, + [IRQ_DA850_T12CMPINT5_3] = 7, + [IRQ_DA850_T12CMPINT6_3] = 7, + [IRQ_DA850_T12CMPINT7_3] = 7, + [IRQ_DA850_RPIINT] = 7, + [IRQ_DA850_VPIFINT] = 7, + [IRQ_DA850_CCINT1] = 7, + [IRQ_DA850_CCERRINT1] = 7, + [IRQ_DA850_TCERRINT2] = 7, + [IRQ_DA850_TINT12_3] = 7, + [IRQ_DA850_TINT34_3] = 7, + [IRQ_DA850_TINTALL_3] = 7, + [IRQ_DA850_MCBSP0RINT] = 7, + [IRQ_DA850_MCBSP0XINT] = 7, + [IRQ_DA850_MCBSP1RINT] = 7, + [IRQ_DA850_MCBSP1XINT] = 7, + [IRQ_DA8XX_ARMCLKSTOPREQ] = 7, +}; + +static struct map_desc da850_io_desc[] = { + { + .virtual = IO_VIRT, + .pfn = __phys_to_pfn(IO_PHYS), + .length = IO_SIZE, + .type = MT_DEVICE + }, + { + .virtual = DA8XX_CP_INTC_VIRT, + .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE), + .length = DA8XX_CP_INTC_SIZE, + .type = MT_DEVICE + }, +}; + +static void __iomem *da850_psc_bases[] = { + IO_ADDRESS(DA8XX_PSC0_BASE), + IO_ADDRESS(DA8XX_PSC1_BASE), +}; + +/* Contents of JTAG ID register used to identify exact cpu type */ +static struct davinci_id da850_ids[] = { + { + .variant = 0x0, + .part_no = 0xb7d1, + .manufacturer = 0x017, /* 0x02f >> 1 */ + .cpu_id = DAVINCI_CPU_ID_DA850, + .name = "da850/omap l138", + }, +}; + +static struct davinci_timer_instance da850_timer_instance[2] = { + { + .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE), + .bottom_irq = IRQ_DA8XX_TINT12_0, + .top_irq = IRQ_DA8XX_TINT34_0, + }, + { + .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE), + .bottom_irq = IRQ_DA8XX_TINT12_1, + .top_irq = IRQ_DA8XX_TINT34_1, + }, +}; + +/* + * T0_BOT: Timer 0, bottom : Used for clock_event & clocksource + * T0_TOP: Timer 0, top : Used by DSP + * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer + */ +static struct davinci_timer_info da850_timer_info = { + .timers = da850_timer_instance, + .clockevent_id = T0_BOT, + .clocksource_id = T0_TOP, +}; + +static struct davinci_soc_info davinci_soc_info_da850 = { + .io_desc = da850_io_desc, + .io_desc_num = ARRAY_SIZE(da850_io_desc), + .jtag_id_base = IO_ADDRESS(DA8XX_JTAG_ID_REG), + .ids = da850_ids, + .ids_num = ARRAY_SIZE(da850_ids), + .cpu_clks = da850_clks, + .psc_bases = da850_psc_bases, + .psc_bases_num = ARRAY_SIZE(da850_psc_bases), + .pinmux_base = IO_ADDRESS(DA8XX_BOOT_CFG_BASE + 0x120), + .pinmux_pins = da850_pins, + .pinmux_pins_num = ARRAY_SIZE(da850_pins), + .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT, + .intc_type = DAVINCI_INTC_TYPE_CP_INTC, + .intc_irq_prios = da850_default_priorities, + .intc_irq_num = DA850_N_CP_INTC_IRQ, + .timer_info = &da850_timer_info, + .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE), + .gpio_num = 128, + .gpio_irq = IRQ_DA8XX_GPIO0, + .serial_dev = &da8xx_serial_device, + .emac_pdata = &da8xx_emac_pdata, +}; + +void __init da850_init(void) +{ + davinci_common_init(&davinci_soc_info_da850); +} diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h index fd41189..189b1ff 100644 --- a/arch/arm/mach-davinci/include/mach/cputype.h +++ b/arch/arm/mach-davinci/include/mach/cputype.h @@ -32,6 +32,7 @@ struct davinci_id { #define DAVINCI_CPU_ID_DM355 0x03550000 #define DAVINCI_CPU_ID_DM365 0x03650000 #define DAVINCI_CPU_ID_DA830 0x08300000 +#define DAVINCI_CPU_ID_DA850 0x08500000 #define IS_DAVINCI_CPU(type, id) \ static inline int is_davinci_ ##type(void) \ @@ -44,6 +45,7 @@ IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467) IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365) IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830) +IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850) #ifdef CONFIG_ARCH_DAVINCI_DM644x #define cpu_is_davinci_dm644x() is_davinci_dm644x() @@ -75,4 +77,10 @@ IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830) #define cpu_is_davinci_da830() 0 #endif +#ifdef CONFIG_ARCH_DAVINCI_DA850 +#define cpu_is_davinci_da850() is_davinci_da850() +#else +#define cpu_is_davinci_da850() 0 +#endif + #endif diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 65b4243..5e47df3 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -38,6 +38,7 @@ #define DA8XX_PSC1_BASE 0x01e27000 void __init da830_init(void); +void __init da850_init(void); int da8xx_register_edma(void); int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); @@ -72,6 +73,13 @@ extern const short da830_ecap2_pins[]; extern const short da830_eqep0_pins[]; extern const short da830_eqep1_pins[]; +extern const short da850_uart0_pins[]; +extern const short da850_uart1_pins[]; +extern const short da850_uart2_pins[]; +extern const short da850_i2c0_pins[]; +extern const short da850_i2c1_pins[]; + int da830_pinmux_setup(const short pins[]); +int da850_pinmux_setup(const short pins[]); #endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h index 735e378..6047c2d 100644 --- a/arch/arm/mach-davinci/include/mach/irqs.h +++ b/arch/arm/mach-davinci/include/mach/irqs.h @@ -340,9 +340,66 @@ #define DA830_N_CP_INTC_IRQ 96 -/* da830 currently has the most gpio pins (128) */ +/* DA850 speicific interrupts */ +#define IRQ_DA850_MPUADDRERR0 27 +#define IRQ_DA850_MPUPROTERR0 27 +#define IRQ_DA850_IOPUADDRERR0 27 +#define IRQ_DA850_IOPUPROTERR0 27 +#define IRQ_DA850_IOPUADDRERR1 27 +#define IRQ_DA850_IOPUPROTERR1 27 +#define IRQ_DA850_IOPUADDRERR2 27 +#define IRQ_DA850_IOPUPROTERR2 27 +#define IRQ_DA850_BOOTCFG_ADDR_ERR 27 +#define IRQ_DA850_BOOTCFG_PROT_ERR 27 +#define IRQ_DA850_MPUADDRERR1 27 +#define IRQ_DA850_MPUPROTERR1 27 +#define IRQ_DA850_IOPUADDRERR3 27 +#define IRQ_DA850_IOPUPROTERR3 27 +#define IRQ_DA850_IOPUADDRERR4 27 +#define IRQ_DA850_IOPUPROTERR4 27 +#define IRQ_DA850_IOPUADDRERR5 27 +#define IRQ_DA850_IOPUPROTERR5 27 +#define IRQ_DA850_MIOPU_BOOTCFG_ERR 27 +#define IRQ_DA850_SATAINT 67 +#define IRQ_DA850_TINT12_2 68 +#define IRQ_DA850_TINT34_2 68 +#define IRQ_DA850_TINTALL_2 68 +#define IRQ_DA850_MMCSDINT0_1 72 +#define IRQ_DA850_MMCSDINT1_1 73 +#define IRQ_DA850_T12CMPINT0_2 74 +#define IRQ_DA850_T12CMPINT1_2 75 +#define IRQ_DA850_T12CMPINT2_2 76 +#define IRQ_DA850_T12CMPINT3_2 77 +#define IRQ_DA850_T12CMPINT4_2 78 +#define IRQ_DA850_T12CMPINT5_2 79 +#define IRQ_DA850_T12CMPINT6_2 80 +#define IRQ_DA850_T12CMPINT7_2 81 +#define IRQ_DA850_T12CMPINT0_3 82 +#define IRQ_DA850_T12CMPINT1_3 83 +#define IRQ_DA850_T12CMPINT2_3 84 +#define IRQ_DA850_T12CMPINT3_3 85 +#define IRQ_DA850_T12CMPINT4_3 86 +#define IRQ_DA850_T12CMPINT5_3 87 +#define IRQ_DA850_T12CMPINT6_3 88 +#define IRQ_DA850_T12CMPINT7_3 89 +#define IRQ_DA850_RPIINT 91 +#define IRQ_DA850_VPIFINT 92 +#define IRQ_DA850_CCINT1 93 +#define IRQ_DA850_CCERRINT1 94 +#define IRQ_DA850_TCERRINT2 95 +#define IRQ_DA850_TINT12_3 96 +#define IRQ_DA850_TINT34_3 96 +#define IRQ_DA850_TINTALL_3 96 +#define IRQ_DA850_MCBSP0RINT 97 +#define IRQ_DA850_MCBSP0XINT 98 +#define IRQ_DA850_MCBSP1RINT 99 +#define IRQ_DA850_MCBSP1XINT 100 + +#define DA850_N_CP_INTC_IRQ 101 + +/* da830/da850 currently has the most gpio pins (128) */ #define DAVINCI_N_GPIO 128 -/* da830 currently has the most irqs so use DA830_N_CP_INTC_IRQ */ -#define NR_IRQS (DA830_N_CP_INTC_IRQ + DAVINCI_N_GPIO) +/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */ +#define NR_IRQS (DA850_N_CP_INTC_IRQ + DAVINCI_N_GPIO) #endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index cce7509..3349fa5 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -704,6 +704,34 @@ enum da830_index { DA830_GPIO2_10, }; +enum davinci_da850_index { + /* UART0 function */ + DA850_NUART0_CTS, + DA850_NUART0_RTS, + DA850_UART0_RXD, + DA850_UART0_TXD, + + /* UART1 function */ + DA850_NUART1_CTS, + DA850_NUART1_RTS, + DA850_UART1_RXD, + DA850_UART1_TXD, + + /* UART2 function */ + DA850_NUART2_CTS, + DA850_NUART2_RTS, + DA850_UART2_RXD, + DA850_UART2_TXD, + + /* I2C1 function */ + DA850_I2C1_SCL, + DA850_I2C1_SDA, + + /* I2C0 function */ + DA850_I2C0_SDA, + DA850_I2C0_SCL, +}; + #ifdef CONFIG_DAVINCI_MUX /* setup pin muxing */ extern int davinci_cfg_reg(unsigned long reg_cfg); diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h index 6b9621d..9528980 100644 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ b/arch/arm/mach-davinci/include/mach/psc.h @@ -177,6 +177,10 @@ #define DA8XX_LPSC1_CR_P3_SS 26 #define DA8XX_LPSC1_L3_CBA_RAM 31 +#define DA850_LPSC1_TPCC1 0 +#define DA850_LPSC1_TPTC2 21 +#define DA850_LPSC1_SATA 8 + extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, unsigned int id, char enable);