[2/6] DaVinci: Adding SPI support in DM365 SOC

Commit Message

[e-mail] July 13, 2009, 4:13 p.m. UTC

From: Sandeep Paulraj <[e-mail]>

The patch adds support for SPI in the DaVinci DM365
SOC.

Signed-off-by: Sandeep Paulraj <[e-mail]>
---
 arch/arm/mach-davinci/dm365.c              |   59 +++++++++++++++++++++++++++-
 arch/arm/mach-davinci/include/mach/dm365.h |    3 +
 2 files changed, 60 insertions(+), 2 deletions(-)

Patch

diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index f02bce8..2e3fb07 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -19,7 +19,7 @@ 
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/gpio.h>
-
+#include <linux/spi/spi.h>
 #include <asm/mach/map.h>
 
 #include <mach/dm365.h>
@@ -32,7 +32,7 @@ 
 #include <mach/time.h>
 #include <mach/serial.h>
 #include <mach/common.h>
-
+#include <mach/spi.h>
 #include "clock.h"
 #include "mux.h"
 
@@ -597,6 +597,61 @@  INT_CFG(DM365,  INT_EMAC_MISCPULSE,  17,    1,    1,     false)
 #endif
 };
 
+static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
+
+static struct davinci_spi_platform_data dm365_spi0_pdata = {
+	.version 	= DAVINCI_SPI_VERSION_1,
+	.num_chipselect = 2,
+	.clk_internal	= 1,
+	.cs_hold	= 1,
+	.intr_level	= 0,
+	.poll_mode	= 1,
+	.c2tdelay	= 8,
+	.t2cdelay	= 8,
+};
+
+static struct resource dm365_spi0_resources[] = {
+	{
+		.start = 0x01c66000,
+		.end   = 0x01c667ff,
+		.flags = IORESOURCE_MEM,
+	},
+	{
+		.start = IRQ_DM365_SPIINT0_0,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device dm365_spi0_device = {
+	.name = "spi_davinci",
+	.id = 0,
+	.dev = {
+		.dma_mask = &dm365_spi0_dma_mask,
+		.coherent_dma_mask = DMA_BIT_MASK(32),
+		.platform_data = &dm365_spi0_pdata,
+	},
+	.num_resources = ARRAY_SIZE(dm365_spi0_resources),
+	.resource = dm365_spi0_resources,
+};
+
+void __init dm365_init_spi0(unsigned chipselect_mask,
+		struct spi_board_info *info, unsigned len)
+{
+	davinci_cfg_reg(DM365_SPI0_SCLK);
+	davinci_cfg_reg(DM365_SPI0_SDI);
+	davinci_cfg_reg(DM365_SPI0_SDO);
+
+	/* not all slaves will be wired up */
+	if (chipselect_mask & BIT(0))
+		davinci_cfg_reg(DM365_SPI0_SDENA0);
+	if (chipselect_mask & BIT(1))
+		davinci_cfg_reg(DM365_SPI0_SDENA1);
+
+	spi_register_board_info(info, len);
+
+	platform_device_register(&dm365_spi0_device);
+}
+
 static struct emac_platform_data dm365_emac_pdata = {
 	.ctrl_reg_offset	= DM365_EMAC_CNTRL_OFFSET,
 	.ctrl_mod_reg_offset	= DM365_EMAC_CNTRL_MOD_OFFSET,
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
index 09db434..61cfd30 100644
--- a/arch/arm/mach-davinci/include/mach/dm365.h
+++ b/arch/arm/mach-davinci/include/mach/dm365.h
@@ -25,5 +25,8 @@ 
 #define DM365_EMAC_CNTRL_RAM_SIZE	(0x2000)
 
 void __init dm365_init(void);
+struct spi_board_info;
+void dm365_init_spi0(unsigned chipselect_mask,
+		struct spi_board_info *info, unsigned len);
 
 #endif /* __ASM_ARCH_DM365_H */