| Message ID | 1247663841-5805-1-git-send-email-s-paulraj@ti.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
On Wednesday 15 July 2009, s-paulraj@ti.com wrote: > +               .modalias       = "at25", > +               .platform_data  = &at25640, > +               .max_speed_hz   = 10 * 1000 * 1000,     /* at 3v3 */ > +               .bus_num        = 0, > +               .chip_select    = 0, > +               .mode           = SPI_MODE_1, My copy of the at26540 data sheet says very explicitly that the chip supports only modes 0 and 3. If it doesn't work when configured for mode 0, you're hiding some kind of driver bug ...
> -----Original Message----- > From: David Brownell [mailto:david-b@pacbell.net] > Sent: Wednesday, July 15, 2009 1:17 PM > To: davinci-linux-open-source@linux.davincidsp.com > Cc: Paulraj, Sandeep > Subject: Re: [PATCH 3/5] DaVinci: DM365: Enabling SPI0 on the DM365 EVM > > On Wednesday 15 July 2009, s-paulraj@ti.com wrote: > > +               .modalias       = "at25", > > +               .platform_data  = &at25640, > > +               .max_speed_hz   = 10 * 1000 * 1000,     /* at 3v3 */ > > +               .bus_num        = 0, > > +               .chip_select    = 0, > > +               .mode           = SPI_MODE_1, > > My copy of the at26540 data sheet says very explicitly that > the chip supports only modes 0 and 3. [Sandeep] so does mine and I've had this question before. 8 months before to be precise. I have checked multiple TI sources(RBL, UBL) across multiple SOC's and even Spectrum Digital code. They all set bit 16 of the SPI format register to 1. That means phase is 1. In our LSPs though we used to set the mode as MODE 0, we used to set the phase to '1' in the driver using a structure we no longer have in the patches I have submitted. When I was verifying SPI on the EVM (not running Linux and just running CCS test programs) long ago, that I have had issues when the phase is not set to '1'. > > If it doesn't work when configured for mode 0, you're hiding > some kind of driver bug ... [Sandeep] or just maybe the DaVinci SPI module expects it that way >
On Wednesday 15 July 2009, Paulraj, Sandeep wrote: > > > > My copy of the at26540 data sheet says very explicitly that > > the chip supports only modes 0 and 3. > > [Sandeep] so does mine and I've had this question before. > 8 months before to be precise. > > I have checked multiple TI sources(RBL, UBL) across multiple SOC's and even > Spectrum Digital code. > They all set bit 16 of the SPI format register to 1. > That means phase is 1. Or more likely, that BIT(16) == !CPOL ... the dm365 SPI docs say for bit 16 0 SPI clock signal is not delayed versus the transmit/receive data stream. The first data bit is transmitted with the first clock edge and the first bit is received with the second (inverse) clock edge. 1 SPI clock signal is delayed by a half SPI clock cycle versus the transmit/receive data stream. The first transmit bit has to output prior to the first clock edge. Master and slave receive the first bit with the first edge. But for example http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus#Clock_polarity_and_phase describes CPOL=0 CPHA=0 as ... data are read on the clock's rising edge (low->high transition) and data are changed on a falling edge (high->low clock transition). Which fits the BIT(16) == !CPOL theory quite nicely, and also matches what the at25640 data sheet timing diagrams show (Figure 3 for mode 0). > When I was verifying SPI on the EVM (not running Linux and just running CCS > test programs) long ago, that I have had issues when the phase is not set > to '1'. Understandable ... it seems BIT(16) == !CPOL, so it must be set. :) - Dave
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index f6adf79..5183323 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -24,6 +24,9 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/nand.h> +#include <linux/spi/spi.h> +#include <linux/spi/eeprom.h> + #include <asm/setup.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -464,6 +467,24 @@ static void __init dm365_evm_map_io(void) dm365_init(); } +static struct spi_eeprom at25640 = { + .byte_len = SZ_64K / 8, + .name = "at25640", + .page_size = 32, + .flags = EE_ADDR2, +}; + +static struct spi_board_info dm365_evm_spi_info[] __initconst = { + { + .modalias = "at25", + .platform_data = &at25640, + .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ + .bus_num = 0, + .chip_select = 0, + .mode = SPI_MODE_1, + }, +}; + static __init void dm365_evm_init(void) { evm_init_i2c(); @@ -476,6 +497,9 @@ static __init void dm365_evm_init(void) /* maybe setup mmc1/etc ... _after_ mmc0 */ evm_init_cpld(); + + dm365_init_spi0(BIT(0), dm365_evm_spi_info, + ARRAY_SIZE(dm365_evm_spi_info)); } static __init void dm365_evm_irq_init(void)