From patchwork Wed Jul 22 11:45:04 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chaithrika@ti.com X-Patchwork-Id: 36812 Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n6MCbrjv014137 for ; Wed, 22 Jul 2009 12:37:53 GMT Received: from dlep33.itg.ti.com ([157.170.170.112]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id n6MCaCeb013503; Wed, 22 Jul 2009 07:36:17 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id n6MCaC0K010178; Wed, 22 Jul 2009 07:36:12 -0500 (CDT) Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 76F4680627; Wed, 22 Jul 2009 07:36:12 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dflp53.itg.ti.com (dflp53.itg.ti.com [128.247.5.6]) by linux.omap.com (Postfix) with ESMTP id 378BB80626 for ; Wed, 22 Jul 2009 07:36:11 -0500 (CDT) Received: from tidmzi-ftp.india.ext.ti.com (localhost [127.0.0.1]) by dflp53.itg.ti.com (8.13.8/8.13.8) with SMTP id n6MCa8Bf020667; Wed, 22 Jul 2009 07:36:09 -0500 (CDT) Received: from symphonyindia.ti.com (symphony-ftp [192.168.247.11]) by tidmzi-ftp.india.ext.ti.com (Postfix) with SMTP id 6298938877; Wed, 22 Jul 2009 18:03:20 +0530 (IST) Received: from localhost.localdomain ([192.168.247.76]) by symphonyindia.ti.com (8.13.1/8.12.10) with ESMTP id n6MCUZYJ025988; Wed, 22 Jul 2009 18:00:35 +0530 From: Chaithrika U S To: alsa-devel@alsa-project.org Date: Wed, 22 Jul 2009 07:45:04 -0400 Message-Id: <1248263104-12142-1-git-send-email-chaithrika@ti.com> X-Mailer: git-send-email 1.5.6 Cc: davinci-linux-open-source@linux.davincidsp.com, broonie@opensource.wolfsonmicro.com Subject: [PATCH] ASoC: tlv320aic3x: Enable PLL when not bypassed X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.4 Precedence: list List-Id: davinci-linux-open-source.linux.davincidsp.com List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: davinci-linux-open-source-bounces@linux.davincidsp.com Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com PLL was not being enabled when it was not bypassed. This patch enables the PLL when it is used. Additionally, it disables the PLL when it is bypassed. Without this patch, the audio on TI DM646x EVM and DM355 EVM does not work properly. The bit clocks and the frame sync signals from the codec are not correct and hence the playback/record are faster than usual for most sample rates. The reason for this was that the PLL was not enabled when it was not bypassed. Tested on DM6467 EVM, playback tested on DM355 EVM. Signed-off-by: Chaithrika U S --- Applies to master branch of ALSA GIT tree at http://git.kernel.org/?p=linux/kernel/git/tiwai/sound-2.6.git;a=summary sound/soc/codecs/tlv320aic3x.c | 11 ++++++++++- 1 files changed, 10 insertions(+), 1 deletions(-) diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c index ab099f4..cb0d1bf 100644 --- a/sound/soc/codecs/tlv320aic3x.c +++ b/sound/soc/codecs/tlv320aic3x.c @@ -767,6 +767,7 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream, int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0; u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1; u16 pll_d = 1; + u8 reg; /* select data word length */ data = @@ -801,8 +802,16 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream, pll_q &= 0xf; aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT); aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV); - } else + /* disable PLL if it is bypassed */ + reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); + aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE); + + } else { aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV); + /* enable PLL when it is used */ + reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); + aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE); + } /* Route Left DAC to left channel input and * right DAC to right channel input */