@@ -306,6 +306,12 @@ static struct clk vpif1_clk = {
.flags = ALWAYS_ENABLED,
};
+static struct clk pci_clk = {
+ .name = "pci",
+ .parent = &pll1_sysclk2,
+ .lpsc = DM646X_LPSC_PCI,
+};
+
struct davinci_clk dm646x_clks[] = {
CLK(NULL, "ref", &ref_clk),
CLK(NULL, "aux", &aux_clkin),
@@ -342,6 +348,7 @@ struct davinci_clk dm646x_clks[] = {
CLK(NULL, "pwm1", &pwm1_clk),
CLK(NULL, "timer0", &timer0_clk),
CLK(NULL, "timer1", &timer1_clk),
+ CLK(NULL, "pci", &pci_clk),
CLK("watchdog", NULL, &timer2_clk),
CLK("palm_bk3710", NULL, &ide_clk),
CLK(NULL, "vpif0", &vpif0_clk),
@@ -409,6 +416,10 @@ static const struct mux_config dm646x_pins[] = {
#ifdef CONFIG_DAVINCI_MUX
MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
+MUX_CFG(DM646X, PCIEN, 0, 0, 7, 4, true)
+
+MUX_CFG(DM646X, HPI32EN, 0, 0, 7, 2, true)
+
MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
@@ -94,6 +94,12 @@ enum davinci_dm646x_index {
/* ATA function */
DM646X_ATAEN,
+ /* PCI function */
+ DM646X_PCIEN,
+
+ /* HPI 32-bit */
+ DM646X_HPI32EN,
+
/* AUDIO Clock */
DM646X_AUDCK1,
DM646X_AUDCK0,
Note that configuration option CONFIG_DAVINCI_RESET_CLOCKS should _not_ be selected if kernel is being built for DM646x PCI target. Slecting this option will disable the PCI PSC during kernel boot, thus preventing any access to PCI backend configuration (e.g., if PCI window needs to be changed). This problem is not applicable when kernel is loaded on Dm646x PCI host since the host setup code would call clk_enable explicitly. Signed-off-by: Hemant Pedanekar <hemantp@ti.com> --- arch/arm/mach-davinci/dm646x.c | 11 +++++++++++ arch/arm/mach-davinci/include/mach/mux.h | 6 ++++++ 2 files changed, 17 insertions(+), 0 deletions(-)