From patchwork Wed Sep 2 16:51:35 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Pedanekar X-Patchwork-Id: 45240 Received: from bear.ext.ti.com (bear.ext.ti.com [192.94.94.41]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n82GrYP9012978 for ; Wed, 2 Sep 2009 16:53:34 GMT Received: from dlep33.itg.ti.com ([157.170.170.112]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id n82GpgCb023051; Wed, 2 Sep 2009 11:51:47 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id n82GpfQi027248; Wed, 2 Sep 2009 11:51:41 -0500 (CDT) Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 0598680627; Wed, 2 Sep 2009 11:51:41 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dbdp31.itg.ti.com (dbdp31.itg.ti.com [172.24.170.98]) by linux.omap.com (Postfix) with ESMTP id E0CCB80626 for ; Wed, 2 Sep 2009 11:51:37 -0500 (CDT) Received: from psplinux051.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id n82GpZRm001730; Wed, 2 Sep 2009 22:21:35 +0530 (IST) Received: from psplinux051.india.ti.com (localhost [127.0.0.1]) by psplinux051.india.ti.com (8.13.1/8.13.1) with ESMTP id n82GpZ1k021768; Wed, 2 Sep 2009 22:21:35 +0530 Received: (from a0393588@localhost) by psplinux051.india.ti.com (8.13.1/8.13.1/Submit) id n82GpZ9b021765; Wed, 2 Sep 2009 22:21:35 +0530 From: Hemant Pedanekar To: davinci-linux-open-source@linux.davincidsp.com Date: Wed, 2 Sep 2009 22:21:35 +0530 Message-Id: <1251910295-21736-1-git-send-email-hemantp@ti.com> X-Mailer: git-send-email 1.6.2.4 Cc: Subject: [PATCH v2] davinci: dm646x-evm: Add platform data for NAND X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.4 Precedence: list List-Id: davinci-linux-open-source.linux.davincidsp.com List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: davinci-linux-open-source-bounces@linux.davincidsp.com Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com This patch adds platform data and partition info for NAND on dm6467 EVM. Note that the partition layout is dependent on the UBL, U-Boot combination used. This patch uses partition organization suitable with latest U-Boot of LSP 1.3. For example, U-Boot environment goes in block 0, UBL resides in block form 1 to 5 and so on. Signed-off-by: Hemant Pedanekar --- Depends on patch "[MTD] [NAND] davinci: fix to use mask_ale from pdata" submitted earlier. Without this patch "No NAND device found" error will be shown on dm6467-evm when booting with NAND enabled in config and NAND won't be accessible. arch/arm/mach-davinci/board-dm646x-evm.c | 82 ++++++++++++++++++++++++++++++ 1 files changed, 82 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 434253e..25a0404 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -34,6 +34,10 @@ #include #include #include +#include +#include +#include + #include #include #include @@ -45,6 +49,7 @@ #include #include #include +#include #include #include @@ -55,6 +60,18 @@ #define HAS_ATA 0 #endif +#if defined(CONFIG_MTD_NAND_DAVINCI) || \ + defined(CONFIG_MTD_NAND_DAVINCI_MODULE) +#define HAS_NAND 1 +#else +#define HAS_NAND 0 +#endif + +#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x20008000 +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000 + +#define NAND_BLOCK_SIZE SZ_128K + /* CPLD Register 0 bits to control ATA */ #define DM646X_EVM_ATA_RST BIT(0) #define DM646X_EVM_ATA_PWD BIT(1) @@ -91,6 +108,69 @@ static struct davinci_uart_config uart_config __initdata = { .enabled_uarts = (1 << 0), }; +/* Note: The partitioning is driven by combination of UBL and U-Boot. For + * example, in the layout below, U-Boot puts environment in block 0 + * and UBL can be in blocks 1-5 while U-Boot resides after UBL blocks. + */ +static struct mtd_partition davinci_nand_partitions[] = { + { + /* U-Boot environment */ + .name = "params", + .offset = 0, + .size = 1 * NAND_BLOCK_SIZE, + .mask_flags = 0, + }, { + /* UBL, U-Boot */ + .name = "bootloader", + .offset = MTDPART_OFS_APPEND, + .size = 10 * NAND_BLOCK_SIZE, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + .mask_flags = 0, + }, { + .name = "filesystem", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + } +}; + +static struct davinci_nand_pdata davinci_nand_data = { + .mask_cle = 0x80000, + .mask_ale = 0x40000, + .parts = davinci_nand_partitions, + .nr_parts = ARRAY_SIZE(davinci_nand_partitions), + .ecc_mode = NAND_ECC_HW, + .options = 0, +}; + +static struct resource davinci_nand_resources[] = { + { + .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, + .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, + .flags = IORESOURCE_MEM, + }, { + .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE, + .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device davinci_nand_device = { + .name = "davinci_nand", + .id = 0, + + .num_resources = ARRAY_SIZE(davinci_nand_resources), + .resource = davinci_nand_resources, + + .dev = { + .platform_data = &davinci_nand_data, + }, +}; + /* CPLD Register 0 Client: used for I/O Control */ static int cpld_reg0_probe(struct i2c_client *client, const struct i2c_device_id *id) @@ -645,6 +725,8 @@ static __init void evm_init(void) dm646x_init_mcasp0(&dm646x_evm_snd_data[0]); dm646x_init_mcasp1(&dm646x_evm_snd_data[1]); + platform_device_register(&davinci_nand_device); + if (HAS_ATA) dm646x_init_ide();