From patchwork Fri Oct 16 19:09:38 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 54383 Received: from bear.ext.ti.com (bear.ext.ti.com [192.94.94.41]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n9GJIhQs012988 for ; Fri, 16 Oct 2009 19:18:43 GMT Received: from dlep33.itg.ti.com ([157.170.170.112]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id n9GJIgkq013816 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Fri, 16 Oct 2009 14:18:43 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id n9GJIfs4023837 for ; Fri, 16 Oct 2009 14:18:41 -0500 (CDT) Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 777C2806CC for ; Fri, 16 Oct 2009 14:17:03 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dflp51.itg.ti.com (dflp51.itg.ti.com [128.247.22.94]) by linux.omap.com (Postfix) with ESMTP id 926DE8062A for ; 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Fri, 16 Oct 2009 19:13:05 +0000 (UTC) Received: from mail-ew0-f220.google.com (209.85.219.220) by VA3EHSMHS015.bigfish.com (10.7.99.25) with Microsoft SMTP Server id 14.0.482.32; Fri, 16 Oct 2009 19:13:03 +0000 Received: by mail-ew0-f220.google.com with SMTP id 20so2500484ewy.40 for ; Fri, 16 Oct 2009 12:13:03 -0700 (PDT) Received: by 10.216.89.10 with SMTP id b10mr669113wef.182.1255720382097; Fri, 16 Oct 2009 12:13:02 -0700 (PDT) Received: from localhost ([216.254.16.51]) by mx.google.com with ESMTPS id i35sm3111028gve.28.2009.10.16.12.12.59 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 16 Oct 2009 12:13:01 -0700 (PDT) From: Kevin Hilman To: linux-arm-kernel@lists.infradead.org Date: Fri, 16 Oct 2009 12:09:38 -0700 Message-ID: <1255720190-7452-36-git-send-email-khilman@deeprootsystems.com> X-Mailer: git-send-email 1.6.4.3 In-Reply-To: <1255720190-7452-35-git-send-email-khilman@deeprootsystems.com> References: <1255720190-7452-1-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-2-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-3-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-4-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-5-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-6-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-7-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-8-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-9-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-10-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-11-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-12-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-13-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-14-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-15-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-16-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-17-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-18-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-19-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-20-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-21-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-22-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-23-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-24-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-25-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-26-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-27-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-28-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-29-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-30-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-31-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-32-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-33-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-34-git-send-email-khilman@deeprootsystems.com> <1255720190-7452-35-git-send-email-khilman@deeprootsystems.com> MIME-Version: 1.0 X-Reverse-DNS: mail-ew0-f220.google.com Cc: davinci-linux-open-source@linux.davincidsp.com Subject: [PATCH 34/46] davinci: DA850/OMAP-L138: add frequency scaling support X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.4 Precedence: list List-Id: davinci-linux-open-source.linux.davincidsp.com List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: davinci-linux-open-source-bounces+patchwork-davinci=patchwork.kernel.org@linux.davincidsp.com Errors-To: davinci-linux-open-source-bounces+patchwork-davinci=patchwork.kernel.org@linux.davincidsp.com diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index a62863c..49dcc71 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -15,6 +15,7 @@ #include #include #include +#include #include @@ -26,6 +27,7 @@ #include #include #include +#include #include "clock.h" #include "mux.h" @@ -40,6 +42,11 @@ #define DA850_REF_FREQ 24000000 #define CFGCHIP3_ASYNC3_CLKSRC BIT(4) +#define CFGCHIP0_PLL_MASTER_LOCK BIT(4) + +static int da850_set_armrate(struct clk *clk, unsigned long rate); +static int da850_round_armrate(struct clk *clk, unsigned long rate); +static int da850_set_pll0rate(struct clk *clk, unsigned long armrate); static struct pll_data pll0_data = { .num = 1, @@ -57,6 +64,7 @@ static struct clk pll0_clk = { .parent = &ref_clk, .pll_data = &pll0_data, .flags = CLK_PLL, + .set_rate = da850_set_pll0rate, }; static struct clk pll0_aux_clk = { @@ -283,6 +291,8 @@ static struct clk arm_clk = { .parent = &pll0_sysclk6, .lpsc = DA8XX_LPSC0_ARM, .flags = ALWAYS_ENABLED, + .set_rate = da850_set_armrate, + .round_rate = da850_round_armrate, }; static struct clk rmii_clk = { @@ -820,6 +830,149 @@ static void da850_set_async3_src(int pllnum) __raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG)); } +#ifdef CONFIG_CPU_FREQ +/* + * Notes: + * According to the TRM, minimum PLLM results in maximum power savings. + * The OPP definitions below should keep the PLLM as low as possible. + * + * The output of the PLLM must be between 400 to 600 MHz. + * This rules out prediv of anything but divide-by-one for 24Mhz OSC input. + */ +struct da850_opp { + unsigned int freq; /* in KHz */ + unsigned int prediv; + unsigned int mult; + unsigned int postdiv; +}; + +static const struct da850_opp da850_opp_300 = { + .freq = 300000, + .prediv = 1, + .mult = 25, + .postdiv = 2, +}; + +static const struct da850_opp da850_opp_200 = { + .freq = 200000, + .prediv = 1, + .mult = 25, + .postdiv = 3, +}; + +static const struct da850_opp da850_opp_96 = { + .freq = 96000, + .prediv = 1, + .mult = 20, + .postdiv = 5, +}; + +#define OPP(freq) \ + { \ + .index = (unsigned int) &da850_opp_##freq, \ + .frequency = freq * 1000, \ + } + +static struct cpufreq_frequency_table da850_freq_table[] = { + OPP(300), + OPP(200), + OPP(96), + { + .index = 0, + .frequency = CPUFREQ_TABLE_END, + }, +}; + +static struct davinci_cpufreq_config cpufreq_info = { + .freq_table = &da850_freq_table[0], +}; + +static struct platform_device da850_cpufreq_device = { + .name = "cpufreq-davinci", + .dev = { + .platform_data = &cpufreq_info, + }, +}; + +int __init da850_register_cpufreq(void) +{ + return platform_device_register(&da850_cpufreq_device); +} + +static int da850_round_armrate(struct clk *clk, unsigned long rate) +{ + int i, ret = 0, diff; + unsigned int best = (unsigned int) -1; + + rate /= 1000; /* convert to kHz */ + + for (i = 0; da850_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { + diff = da850_freq_table[i].frequency - rate; + if (diff < 0) + diff = -diff; + + if (diff < best) { + best = diff; + ret = da850_freq_table[i].frequency; + } + } + + return ret * 1000; +} + +static int da850_set_armrate(struct clk *clk, unsigned long index) +{ + struct clk *pllclk = &pll0_clk; + + return clk_set_rate(pllclk, index); +} + +static int da850_set_pll0rate(struct clk *clk, unsigned long index) +{ + unsigned int prediv, mult, postdiv; + struct da850_opp *opp; + struct pll_data *pll = clk->pll_data; + unsigned int v; + int ret; + + opp = (struct da850_opp *) da850_freq_table[index].index; + prediv = opp->prediv; + mult = opp->mult; + postdiv = opp->postdiv; + + /* Unlock writing to PLL registers */ + v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG)); + v &= ~CFGCHIP0_PLL_MASTER_LOCK; + __raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG)); + + ret = davinci_set_pllrate(pll, prediv, mult, postdiv); + if (WARN_ON(ret)) + return ret; + + return 0; +} +#else +int __init da850_register_cpufreq(void) +{ + return 0; +} + +static int da850_set_armrate(struct clk *clk, unsigned long rate) +{ + return -EINVAL; +} + +static int da850_set_pll0rate(struct clk *clk, unsigned long armrate) +{ + return -EINVAL; +} + +static int da850_round_armrate(struct clk *clk, unsigned long rate) +{ + return clk->rate; +} +#endif + static struct davinci_soc_info davinci_soc_info_da850 = { .io_desc = da850_io_desc, .io_desc_num = ARRAY_SIZE(da850_io_desc), diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 3b75273..401bf93 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -37,6 +37,7 @@ extern void __iomem *da8xx_syscfg_base; #define DA8XX_SYSCFG_BASE (IO_PHYS + 0x14000) #define DA8XX_SYSCFG_VIRT(x) (da8xx_syscfg_base + (x)) #define DA8XX_JTAG_ID_REG 0x18 +#define DA8XX_CFGCHIP0_REG 0x17c #define DA8XX_CFGCHIP2_REG 0x184 #define DA8XX_CFGCHIP3_REG 0x188 @@ -85,6 +86,7 @@ int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata); int da8xx_register_mmcsd0(struct davinci_mmc_config *config); void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata); int da8xx_register_rtc(void); +int da850_register_cpufreq(void); extern struct platform_device da8xx_serial_device; extern struct emac_platform_data da8xx_emac_pdata;