From patchwork Wed Oct 21 15:48:24 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sekhar Nori X-Patchwork-Id: 55138 Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n9LFqaXZ031236 for ; Wed, 21 Oct 2009 15:52:37 GMT Received: from dlep35.itg.ti.com ([157.170.170.118]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id n9LFmgfm006906 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 21 Oct 2009 10:48:42 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id n9LFmegi019458; Wed, 21 Oct 2009 10:48:40 -0500 (CDT) Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 90EFB8062E; Wed, 21 Oct 2009 10:48:39 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dbdp31.itg.ti.com (dbdp31.itg.ti.com [172.24.170.98]) by linux.omap.com (Postfix) with ESMTP id 5708B8062A for ; Wed, 21 Oct 2009 10:48:27 -0500 (CDT) Received: from psplinux051.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id n9LFmOwb027405; Wed, 21 Oct 2009 21:18:25 +0530 (IST) Received: from psplinux051.india.ti.com (localhost [127.0.0.1]) by psplinux051.india.ti.com (8.13.1/8.13.1) with ESMTP id n9LFmO64015725; Wed, 21 Oct 2009 21:18:24 +0530 Received: (from a0875516@localhost) by psplinux051.india.ti.com (8.13.1/8.13.1/Submit) id n9LFmOsg015722; Wed, 21 Oct 2009 21:18:24 +0530 From: Sekhar Nori To: davinci-linux-open-source@linux.davincidsp.com Date: Wed, 21 Oct 2009 21:18:24 +0530 Message-Id: <1256140104-15606-5-git-send-email-nsekhar@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: <1256140104-15606-4-git-send-email-nsekhar@ti.com> References: <1256140104-15606-1-git-send-email-nsekhar@ti.com> <1256140104-15606-2-git-send-email-nsekhar@ti.com> <1256140104-15606-3-git-send-email-nsekhar@ti.com> <1256140104-15606-4-git-send-email-nsekhar@ti.com> Cc: Subject: [PATCH 5/5] davinci: DA850/OMAP-L138 EVM: simplify configuration of emac in MII/RMII mode X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.4 Precedence: list List-Id: davinci-linux-open-source.linux.davincidsp.com List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: davinci-linux-open-source-bounces@linux.davincidsp.com Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index fd6f780..d0e3178 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -535,23 +535,27 @@ static int __init da850_evm_config_emac(void) cfg_chip3_base = DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG); - /* configure the CFGCHIP3 register for RMII or MII */ val = __raw_readl(cfg_chip3_base); - if (rmii_en) + + if (rmii_en) { val |= BIT(8); - else + ret = da8xx_pinmux_setup(da850_rmii_pins); + pr_info("EMAC: RMII PHY configured, MII PHY will not be" + " functional\n"); + } else { val &= ~BIT(8); - - __raw_writel(val, cfg_chip3_base); - - if (!rmii_en) ret = da8xx_pinmux_setup(da850_cpgmac_pins); - else - ret = da8xx_pinmux_setup(da850_rmii_pins); + pr_info("EMAC: MII PHY configured, RMII PHY will not be" + " functional\n"); + } + if (ret) pr_warning("da850_evm_init: cpgmac/rmii mux setup failed: %d\n", ret); + /* configure the CFGCHIP3 register for RMII or MII */ + __raw_writel(val, cfg_chip3_base); + ret = davinci_cfg_reg(DA850_GPIO2_6); if (ret) pr_warning("da850_evm_init:GPIO(2,6) mux setup " @@ -564,17 +568,8 @@ static int __init da850_evm_config_emac(void) return ret; } - if (rmii_en) { - /* Disable MII MDIO clock */ - gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, 1); - pr_info("EMAC: RMII PHY configured, MII PHY will not be" - " functional\n"); - } else { - /* Enable MII MDIO clock */ - gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, 0); - pr_info("EMAC: MII PHY configured, RMII PHY will not be" - " functional\n"); - } + /* Enable/Disable MII MDIO clock */ + gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, rmii_en); soc_info->emac_pdata->phy_mask = DA850_EVM_PHY_MASK; soc_info->emac_pdata->mdio_max_freq = DA850_EVM_MDIO_FREQUENCY;