From patchwork Wed Jan 6 18:31:44 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 71366 Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by demeter.kernel.org (8.14.3/8.14.2) with ESMTP id o06IZV5L013798 for ; Wed, 6 Jan 2010 18:35:32 GMT Received: from dlep33.itg.ti.com ([157.170.170.112]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o06IXekE011714 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 6 Jan 2010 12:33:41 -0600 Received: from linux.omap.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o06IXdaj020386; Wed, 6 Jan 2010 12:33:39 -0600 (CST) Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 8ED818062B; Wed, 6 Jan 2010 12:33:39 -0600 (CST) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dflp53.itg.ti.com (dflp53.itg.ti.com [128.247.5.6]) by linux.omap.com (Postfix) with ESMTP id E0F5A8062C for ; Wed, 6 Jan 2010 12:32:24 -0600 (CST) Received: from medina.ext.ti.com (localhost [127.0.0.1]) by dflp53.itg.ti.com (8.13.8/8.13.8) with ESMTP id o06IWOBQ008909 for ; Wed, 6 Jan 2010 12:32:24 -0600 (CST) Received: from psmtp.com (na3sys009amx236.postini.com [74.125.149.120]) by medina.ext.ti.com (8.13.7/8.13.7) with SMTP id o06IWOPR019081 for ; Wed, 6 Jan 2010 12:32:24 -0600 Received: from source ([209.85.216.189]) by na3sys009amx236.postini.com ([74.125.148.10]) with SMTP; Wed, 06 Jan 2010 12:32:24 CST Received: by pxi27 with SMTP id 27so11129937pxi.4 for ; Wed, 06 Jan 2010 10:32:23 -0800 (PST) Received: by 10.140.83.35 with SMTP id g35mr2162197rvb.296.1262802743540; Wed, 06 Jan 2010 10:32:23 -0800 (PST) Received: from localhost (deeprootsystems.com [216.254.16.51]) by mx.google.com with ESMTPS id 21sm17217121pzk.3.2010.01.06.10.32.22 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 06 Jan 2010 10:32:22 -0800 (PST) From: Kevin Hilman To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 02/35] davinci: move PLL wait time values to clock.h Date: Wed, 6 Jan 2010 10:31:44 -0800 Message-Id: <1262802737-6601-3-git-send-email-khilman@deeprootsystems.com> X-Mailer: git-send-email 1.6.6.rc2.1.g42108 In-Reply-To: <1262802737-6601-2-git-send-email-khilman@deeprootsystems.com> References: <1262802737-6601-1-git-send-email-khilman@deeprootsystems.com> <1262802737-6601-2-git-send-email-khilman@deeprootsystems.com> X-pstn-neptune: 0/0/0.00/0 X-pstn-levels: (S:80.99114/99.90000 CV:99.9000 FC:95.5390 LC:95.5390 R:95.9108 P:95.9108 M:97.0282 C:98.6951 ) X-pstn-settings: 2 (0.5000:0.5000) s cv gt3 gt2 gt1 X-pstn-addresses: from [db-null] Cc: davinci-linux-open-source@linux.davincidsp.com X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: davinci-linux-open-source-bounces@linux.davincidsp.com Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index baece65..0fa68c5 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -376,7 +376,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, locktime = ((2000 * prediv) / 100); prediv = (prediv - 1) | PLLDIV_EN; } else { - locktime = 20; + locktime = PLL_LOCK_TIME; } if (postdiv) postdiv = (postdiv - 1) | PLLDIV_EN; @@ -389,12 +389,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); __raw_writel(ctrl, pll->base + PLLCTL); - /* - * Wait for 4 OSCIN/CLKIN cycles to ensure that the PLLC has switched - * to bypass mode. Delay of 1us ensures we are good for all > 4MHz - * OSCIN/CLKIN inputs. Typically the input is ~25MHz. - */ - udelay(1); + udelay(PLL_BYPASS_TIME); /* Reset and enable PLL */ ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS); @@ -408,11 +403,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, if (pll->flags & PLL_HAS_POSTDIV) __raw_writel(postdiv, pll->base + POSTDIV); - /* - * Wait for PLL to reset properly, OMAP-L138 datasheet says - * 'min' time = 125ns - */ - udelay(1); + udelay(PLL_RESET_TIME); /* Bring PLL out of reset */ ctrl |= PLLCTL_PLLRST; diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index c92d77a..eca4d99 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -53,6 +53,21 @@ #define PLLDIV_EN BIT(15) #define PLLDIV_RATIO_MASK 0x1f +/* + * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN + * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us + * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input + * is ~25MHz. Units are micro seconds. + */ +#define PLL_BYPASS_TIME 1 +/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */ +#define PLL_RESET_TIME 1 +/* + * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4 + * Units are micro seconds. + */ +#define PLL_LOCK_TIME 20 + struct pll_data { u32 phys_base; void __iomem *base;